1 ; MMURTL Operating System Source Code
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2 ; Copyright 1991,1992,1993,1994 Richard A. Burgess
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3 ; ALL RIGHTS RESERVED Version 1.0
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8 ;=============================================================================
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10 ; This sets IRQ00-0F vectors in the 8259s
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11 ; to be Int20 thru 2F.
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13 ; When the PICUs are initialized, all the hardware interrupts are MASKED.
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14 ; Each driver that uses a hardware interrupt(s) is responsible
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15 ; for unmasking that particular IRQ.
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22 OUT PICU1+0,AL ;ICW1 - MASTER
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25 OUT PICU2+0,AL ;ICW1 - SLAVE
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29 OUT PICU1+1,AL ;ICW2 - MASTER
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33 OUT PICU2+1,AL ;ICW2 - SLAVE
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37 OUT PICU1+1,AL ;ICW3 - MASTER
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41 OUT PICU2+1,AL ;ICW3 - SLAVE
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45 OUT PICU1+1,AL ;ICW4 - MASTER
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48 OUT PICU2+1,AL ;ICW4 - SLAVE
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51 MOV AL,11111010b ;Masked all but cascade/timer
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52 ; MOV AL,01000000b ;Floppy masked
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53 OUT PICU1+1,AL ;MASK - MASTER (0= Ints ON)
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58 OUT PICU2+1,AL ;MASK - SLAVE
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63 ;=====================================================
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64 ;The following PUBLIC FAR calls support ISR operations:
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66 ; SetIRQVector(IRQnum, pVector)
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67 ; GetIRQVector(IRQnum, pVectorRet)
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72 ; In each case, IRQnum is the hardware interrupt request number for the
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73 ; IRQ served. This will be 0-7 for interrupts on 8259 #1 and 8-15 for
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74 ; interrupts on 8259 #2. The predetermined IRQ uses are:
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77 ; IRQ 1 Keyboard (8042)
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78 ; IRQ 2 Cascade from PICU2 (handled internally)
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79 ; IRQ 3 COMM 2 Serial port
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80 ; IRQ 4 COMM 1 Serial port
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81 ; IRQ 5 Line Printer 2
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82 ; IRQ 6 Floppy disk controller
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83 ; IRQ 7 Line Printer 1
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90 ; IRQ 13 Math coprocessor
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91 ; IRQ 14 Hard disk controller
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94 ;=============================================================================
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96 ; SetIntVector(IRQNum, pISR)
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97 ; This sets a 32 bit offset for an interrupt handler
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98 ; that services one of the hardware interrupts. (0-15)
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99 ; The ISR MUST reside in the OS Code segment. This means that only
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100 ; device drivers or the OS can set and service interrupts!!
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101 ; The DPL is set to 3 (all code can be hardware interrupted).
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103 PUBLIC __SetIRQVector:
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106 MOV ECX, [EBP+16] ;Get IRQ number (0-15)
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107 AND ECX, 0Fh ;0 to 15 max!
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108 ADD ECX, 20h ;INT number is set for IRQ
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109 MOV EAX, 08E00h ;Int gate description
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110 MOV EBX, OSCodeSel ;
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111 MOV ESI, [EBP+12] ;
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112 CALL FWORD PTR _AddIDTGate ;
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117 ;=============================================================================
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119 ; GetIntVector(IRQNum, pVectorRet)
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120 ; This returns the vector (offset) of the ISR that is currently
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123 PUBLIC __GetIRQVector:
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130 ;=============================================================================
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132 ; Sends End Of Interrupt to PICU (or Both) based on IRQ number (0-15)
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133 ; If IRQnum is 0-7 then we send to 1, else we send to 1 then 2.
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139 MOV EAX, [EBP+0Ch] ;Get IRQ number (0-15)
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143 CMP AH, 7 ;PICU1 only?
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145 OUT PICU2,AL ;Send to 2 also
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152 ;===============================================
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153 ; MaskIRQ(IRQnum) masks the IRQ number specified (0-15).
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154 ; The proper PICU is selected based on the IRQ number.
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164 MOV ECX, [EBP+0Ch] ;Get IRQ number (0-15)
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165 AND ECX, 0Fh ;(0-15)
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166 SHL EAX, CL ;Set the bit for the IRQ (0-7) or (8-15)
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177 IN AL, PICU2+1 ;AH already has correct value
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185 POPFD ;Give em their flags back
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189 ;===============================================
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190 ; UnMaskIRQ(IRQnum) UNmasks the IRQ number specified (0-15).
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191 ; The proper PICU is selected based on the IRQ number.
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193 PUBLIC __UnMaskIRQ:
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197 CLI ;Previous state is reset on POPFD
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201 MOV ECX,[EBP+0Ch] ;Get IRQ number (0-15)
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202 AND ECX, 0Fh ; (0-15 only)
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203 SHL EAX, CL ;Set the bit for the IRQ (0-7)
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229 ;===== Module End ================
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