--- /dev/null
+/* 386 D-Group ASSEMBLER. Header file.\r
+ Copyright 1992 R.A. Burgess\r
+*/\r
+\r
+ /* The DASM parser returns a TOKEN type and fills in certain\r
+ global variables with the values found. The token type is\r
+ placed in Token as well as being returned to the caller.\r
+*/\r
+\r
+/* The following are the TOKEN types returned by the parser or\r
+ the expression analyzer :\r
+*/\r
+\r
+#define ZERO 0 /* Parser returned NOTHING (blank or EOL) */\r
+#define INSTRU 1 /* 386 instruction. Number placed in TInst. */\r
+#define REGIST 2 /* 386 register is placed in TReg */\r
+#define SYMBOL 3 /* In symbol table. Sym number placed in TSymnum */\r
+#define LSYMBOL 4 /* In symbol table. LSym number placed in TSymnum */\r
+#define STRING 5 /* 'quoted' string of characters left in TString */\r
+#define NUMBER 6 /* Valid value placed in TNumber */\r
+#define NUMOFF 7 /* Valid TNumber derived from OFFSET (needs fix) */\r
+#define UNKSYM 8 /* Qualifies as a sym but not found. Left in TString */\r
+#define SYMOFF 9 /* Symbol offset value (from Expression analyzer) */\r
+#define ERROR 10 /* Bad char found in line. Line terminated by Parse(). */\r
+\r
+/* alphabetized list of reserved words excluding registers and\r
+ instructions. They must be alphabetized for binary search\r
+ function to work. They begin with #89 so they don't conflict\r
+ with other token values. */\r
+\r
+#define nreserved 30\r
+#define srsvd 8 /* size of a reserved storage */\r
+#define nrsvd1 94 /* must be the first number of rgReserved */\r
+char rgReserved[nreserved][srsvd] = { /* 109 bytes */\r
+ "ALIGN", /* 94 */\r
+ "BYTE", /* 95 */\r
+ "CODE", /* 96 */\r
+ "DATA", /* 97 */\r
+ "DB", /* 98 */\r
+ "DD", /* 99 */\r
+ "DF", /* 100 */\r
+ "DUP", /* 101 */\r
+ "DW", /* 102 */\r
+ "DWORD", /* 103 */\r
+ "END", /* 104 */\r
+ "EQU", /* 105 */\r
+ "EXTRN", /* 106 */\r
+ "FAR", /* 107 */\r
+ "FWORD", /* 108 */\r
+ "INCLUDE", /* 109 */\r
+ "NAME", /* 110 */\r
+ "NEAR", /* 111 */\r
+ "OFFSET", /* 112 */\r
+ "PARA", /* 113 */\r
+ "PTR", /* 114 */\r
+ "PUBLIC", /* 115 */\r
+ "SEARCH", /* 116 */\r
+ "SHORT", /* 117 */\r
+ "STACK", /* 118 */\r
+ "START", /* 119 */\r
+ "USE16", /* 120 */\r
+ "USE32", /* 121 */\r
+ "VIRTUAL", /* 122 */\r
+ "WORD", /* 123 up to 127 MAX */\r
+ };\r
+\r
+/* The following reserved "words" are recognized by Parse.\r
+ This list MUST agree with the numbering of the table\r
+ rgReserved above.\r
+*/\r
+\r
+#define rALIGN 94 /* .ALIGN n - Align code segment */\r
+#define rBYTE 95 /* for forcing types on operands */\r
+#define rCODE 96 /* .CODE - begin/continue code segment */\r
+#define rDATA 97 /* .DATA - begin/continue data segment */\r
+#define rDB 98 /* storage of byte(s) or (strings) */\r
+#define rDD 99 /* double words */\r
+#define rDF 100 /* FWord (OFF:SEL) */\r
+#define rDUP 101 /* duplicated storage of DB, DW or DD */\r
+#define rDW 102 /* storage of words follows */\r
+#define rDWORD 103 /* for forcing types on operands */\r
+#define rEND 104 /* .END - file end - no more segments */\r
+#define rEQU 105 /* EQUATE for numbers/addresses only */\r
+#define rEXTRN 106 /* for EXTERNAL definition */\r
+#define rFAR 107 /* FAR operator for calls */\r
+#define rFWORD 108 /* for forcing types on operands */\r
+#define rINCLUDE 109 /* .INCLUDE - Include file for assembly */\r
+#define rNAME 110 /* .NAME to name a segment */\r
+#define rNEAR 111 /* NEAR operator for calls (default) */\r
+#define rOFFSET 112 /* offset in segment of ... */\r
+#define rPARA 113 /* PTR operator for mem ops */\r
+#define rPTR 114 /* PTR operator for mem ops */\r
+#define rPUBLIC 115 /* for PUBLIC declarations */\r
+#define rSEARCH 116 /* SEARCH command for Lib files */\r
+#define rSHORT 117 /* SHORT operator for relative jumps */\r
+#define rSTACK 118 /* .START - Entry point for execution */\r
+#define rSTART 119 /* .STACK - Sets initial stack size */\r
+#define rUSE16 120 /* .USE16 (16 bit segment) */\r
+#define rUSE32 121 /* .USE16 (16 bit segment) */\r
+#define rVIRTUAL 122 /* .VIRTUAL n - Data @ virtual address n */\r
+#define rWORD 123 /* WORD operator for mem ops */\r
+\r
+/* Special characters. They are treated as reserved words but are\r
+ not searched alphabetically. They must maintain their ASCII\r
+ values (other tokens are numbers "around" them).\r
+*/\r
+\r
+#define DOLLAR 0x24 /* 36 */\r
+#define SQUOTE 0x27 /* 39 */\r
+#define OPENRND 0x28 /* 40 */\r
+#define CLOSRND 0x29 /* 41 */\r
+#define STAR 0x2a /* 42 */\r
+#define PLUS 0x2b /* 43 */\r
+#define COMMA 0x2c /* 44 */\r
+#define MINUS 0x2d /* 45 */\r
+#define DOT 0x2e /* 46 */\r
+#define SLASH 0x2f /* 47 */\r
+#define COLON 0x3a /* 58 */\r
+#define SEMI 0x3b /* 59 */\r
+#define OPENSQR 0x5b /* 91 */\r
+#define CLOSSQR 0x5d /* 93 */\r
+\r
+/* The following bits identify symbol types in GST & LST */\r
+\r
+#define CLABEL 0x0001 /* Code label - SymPtr has Offset in Code seg */\r
+#define DLABEL 0x0002 /* Data label - SymPtr has Offset in Data seg */\r
+#define MACRO 0x0004 /* No offset associated - pts to string */\r
+#define sBYTE 0x0008 /* Data label for BYTE (8 bit) */\r
+#define sWORD 0x0010 /* Data label for WORD (16 bit) */\r
+#define sDWORD 0x0020 /* Data label for DWORD (32 bit) */\r
+#define sFWORD 0x0040 /* Data label for FWORD (48 bit) */\r
+#define tEXTRN 0x0080 /* Defined External, Public not found yet */\r
+#define tFAR 0x0100 /* Defined as FAR, default is near */\r
+#define tPUBLIC 0x0200 /* Defined as PUBLIC */\r
+\r
+\r
+/* This is an alphabetical array of all the 386 registers.\r
+ It it used for a binary search for a register name. If\r
+ the beginning number (128) is changed here you must make\r
+ sure to change the define nreg1 to match to the search\r
+ routine will give you the correct number They start at 128\r
+ so they don't conflict with operand types in instruction table\r
+ rgINS[].\r
+*/\r
+\r
+#define nregs 52\r
+#define sregs 4\r
+#define nreg1 128\r
+\r
+char rgreg[nregs][4] = { /* 176 bytes */\r
+\r
+ "AH", /* 128 */\r
+ "AL", /* 129 */\r
+ "AX", /* 130 */\r
+ "BH", /* 131 */\r
+ "BL", /* 132 */\r
+ "BP", /* 133 */\r
+ "BX", /* 134 */\r
+ "CH", /* 135 */\r
+ "CL", /* 136 */\r
+ "CR0", /* 137 */\r
+ "CR1", /* 138 */\r
+ "CR2", /* 139 */\r
+ "CR3", /* 140 */\r
+ "CS", /* 141 */\r
+ "CX", /* 142 */\r
+ "DH", /* 143 */\r
+ "DI", /* 144 */\r
+ "DL", /* 145 */\r
+ "DR0", /* 146 */\r
+ "DR1", /* 147 */\r
+ "DR2", /* 148 */\r
+ "DR3", /* 149 */\r
+ "DR6", /* 150 */\r
+ "DR7", /* 151 */\r
+ "DS", /* 152 */\r
+ "DX", /* 153 */\r
+ "EAX", /* 154 */\r
+ "EBP", /* 155 */\r
+ "EBX", /* 156 */\r
+ "ECX", /* 157 */\r
+ "EDI", /* 158 */\r
+ "EDX", /* 159 */\r
+ "ESI", /* 160 */\r
+ "ES", /* 161 */\r
+ "ESP", /* 162 */\r
+ "FS", /* 163 */\r
+ "GS", /* 164 */\r
+ "SI", /* 165 */\r
+ "SP", /* 166 */\r
+ "SS", /* 167 */\r
+ "TR6", /* 168 */\r
+ "TR7"}; /* 169 */\r
+\r
+#define rAH 128\r
+#define rAL 129\r
+#define rAX 130\r
+#define rBH 131\r
+#define rBL 132\r
+#define rBP 133\r
+#define rBX 134\r
+#define rCH 135\r
+#define rCL 136\r
+#define rCR0 137\r
+#define rCR1 138\r
+#define rCR2 139\r
+#define rCR3 140\r
+#define rCS 141\r
+#define rCX 142\r
+#define rDH 143\r
+#define rDI 144\r
+#define rDL 145\r
+#define rDR0 146\r
+#define rDR1 147\r
+#define rDR2 148\r
+#define rDR3 149\r
+#define rDR6 150\r
+#define rDR7 151\r
+#define rDS 152\r
+#define rDX 153\r
+#define rEAX 154\r
+#define rEBP 155\r
+#define rEBX 156\r
+#define rECX 157\r
+#define rEDI 158\r
+#define rEDX 159\r
+#define rESI 160\r
+#define rES 161\r
+#define rESP 162\r
+#define rFS 163\r
+#define rGS 164\r
+#define rSI 165\r
+#define rSP 166\r
+#define rSS 167\r
+#define rTR6 168\r
+#define rTR7 169\r
+\r
+/* This is an alaphebetical array of all the 386 instructions */\r
+/* It it used for a binary search for an instruction */\r
+\r
+#define ninst 208\r
+#define sinst 7 /* size of a instruction storage */\r
+\r
+int rgInsLookUp[ninst+1]; /* Lookup for instruction table */\r
+\r
+char rginst[ninst][sinst] = { /* 1456 bytes */\r
+\r
+ "AAA", /* 001 */\r
+ "AAD", /* 002 */\r
+ "AAM", /* 003 */\r
+ "AAS", /* 004 */\r
+ "ADC", /* 005 */\r
+ "ADD", /* 006 */\r
+ "AND", /* 007 */\r
+ "ARPL", /* 008 */\r
+\r
+ "BOUND", /* 009 */\r
+ "BSF", /* 010 */\r
+ "BSR", /* 011 */\r
+ "BT", /* 012 */\r
+ "BTC", /* 013 */\r
+ "BTR", /* 014 */\r
+ "BTS", /* 015 */\r
+\r
+ "CALL", /* 016 */\r
+ "CBW", /* 017 */\r
+ "CDQ", /* 018 */\r
+ "CLC", /* 019 */\r
+ "CLD", /* 020 */\r
+ "CLI", /* 021 */\r
+ "CLTS", /* 022 */\r
+ "CMC", /* 023 */\r
+ "CMP", /* 024 */\r
+ "CMPS", /* 025 */\r
+ "CMPSB", /* 026 */\r
+ "CMPSD", /* 027 */\r
+ "CMPSW", /* 028 */\r
+ "CWD", /* 029 */\r
+ "CWDE", /* 030 */\r
+\r
+ "DAA", /* 031 */\r
+ "DAS", /* 032 */\r
+ "DEC", /* 033 */\r
+ "DIV", /* 034 */\r
+\r
+ "ENTER", /* 035 */\r
+\r
+ "HLT", /* 036 */\r
+\r
+ "IDIV", /* 037 */\r
+ "IMUL", /* 038 */\r
+ "IN", /* 039 */\r
+ "INC", /* 040 */\r
+ "INS", /* 041 */\r
+ "INSB", /* 042 */\r
+ "INSD", /* 043 */\r
+ "INSW", /* 044 */\r
+ "INT", /* 045 */\r
+ "INTO", /* 046 */\r
+ "IRET", /* 047 */\r
+ "IRETD", /* 048 */\r
+\r
+ "JA", /* 049 */\r
+ "JAE", /* 050 */\r
+ "JB", /* 051 */\r
+ "JBE", /* 052 */\r
+ "JC", /* 053 */\r
+ "JCXZ", /* 054 */\r
+ "JE", /* 055 */\r
+ "JECXZ", /* 056 */\r
+ "JG", /* 057 */\r
+ "JGE", /* 058 */\r
+ "JL", /* 059 */\r
+ "JLE", /* 060 */\r
+ "JMP", /* 061 */\r
+ "JNA", /* 062 */\r
+ "JNAE", /* 063 */\r
+ "JNB", /* 064 */\r
+ "JNBE", /* 065 */\r
+ "JNC", /* 066 */\r
+ "JNE", /* 067 */\r
+ "JNG", /* 068 */\r
+ "JNGE", /* 069 */\r
+ "JNL", /* 070 */\r
+ "JNLE", /* 071 */\r
+ "JNO", /* 072 */\r
+ "JNP", /* 073 */\r
+ "JNS", /* 074 */\r
+ "JNZ", /* 075 */\r
+ "JO", /* 076 */\r
+ "JP", /* 077 */\r
+ "JPE", /* 078 */\r
+ "JPO", /* 079 */\r
+ "JS", /* 080 */\r
+ "JZ", /* 081 */\r
+\r
+ "LAHF", /* 082 */\r
+ "LAR", /* 083 */\r
+ "LDS", /* 084 */\r
+ "LEA", /* 085 */\r
+ "LEAVE", /* 086 */\r
+ "LES", /* 087 */\r
+ "LFS", /* 088 */\r
+ "LGDT", /* 089 */\r
+ "LGS", /* 090 */\r
+ "LIDT", /* 091 */\r
+ "LLDT", /* 092 */\r
+ "LMSW", /* 093 */\r
+ "LOCK", /* 094 */\r
+ "LODS", /* 095 */\r
+ "LODSB", /* 096 */\r
+ "LODSD", /* 097 */\r
+ "LODSW", /* 098 */\r
+ "LOOP", /* 099 */\r
+ "LOOPE", /* 100 */\r
+ "LOOPNE", /* 101 */\r
+ "LOOPNZ", /* 102 */\r
+ "LOOPZ", /* 103 */\r
+ "LSL", /* 104 */\r
+ "LSS", /* 105 */\r
+ "LTR", /* 106 */\r
+\r
+ "MOV", /* 107 */\r
+ "MOVS", /* 108 */\r
+ "MOVSB", /* 109 */\r
+ "MOVSD", /* 110 */\r
+ "MOVSW", /* 111 */\r
+ "MOVSX", /* 112 */\r
+ "MOVZX", /* 113 */\r
+ "MUL", /* 114 */\r
+\r
+ "NEG", /* 115 */\r
+ "NOP", /* 116 */\r
+ "NOT", /* 117 */\r
+\r
+ "OR", /* 118 */\r
+ "OUT", /* 119 */\r
+ "OUTS", /* 120 */\r
+ "OUTSB", /* 121 */\r
+ "OUTSD", /* 122 */\r
+ "OUTSW", /* 123 */\r
+\r
+ "POP", /* 124 */\r
+ "POPA", /* 125 */\r
+ "POPAD", /* 126 */\r
+ "POPF", /* 127 */\r
+ "POPFD", /* 128 */\r
+ "PUSH", /* 129 */\r
+ "PUSHA", /* 130 */\r
+ "PUSHAD", /* 131 */\r
+ "PUSHF", /* 132 */\r
+ "PUSHFD", /* 133 */\r
+\r
+ "RCL", /* 134 */\r
+ "RCR", /* 135 */\r
+ "REP", /* 136 */\r
+ "REPE", /* 137 */\r
+ "REPNE", /* 138 */\r
+ "REPNZ", /* 139 */\r
+ "REPZ", /* 140 */\r
+ "RET", /* 141 */\r
+ "RETF", /* 142 */\r
+ "RETN", /* 143 */\r
+ "ROL", /* 144 */\r
+ "ROR", /* 145 */\r
+\r
+ "SAHF", /* 146 */\r
+ "SAL", /* 147 */\r
+ "SAR", /* 148 */\r
+ "SBB", /* 149 */\r
+ "SCAS", /* 150 */\r
+ "SCASB", /* 151 */\r
+ "SCASD", /* 152 */\r
+ "SCASW", /* 153 */\r
+ "SETA", /* 154 */\r
+ "SETAE", /* 155 */\r
+ "SETB", /* 156 */\r
+ "SETBE", /* 157 */\r
+ "SETC", /* 158 */\r
+ "SETE", /* 159 */\r
+ "SETG", /* 160 */\r
+ "SETGE", /* 161 */\r
+ "SETL", /* 162 */\r
+ "SETLE", /* 163 */\r
+ "SETNA", /* 164 */\r
+ "SETNAE", /* 165 */\r
+ "SETNB", /* 166 */\r
+ "SETNBE", /* 167 */\r
+ "SETNC", /* 168 */\r
+ "SETNE", /* 169 */\r
+ "SETNG", /* 170 */\r
+ "SETNGE", /* 171 */\r
+ "SETNL", /* 172 */\r
+ "SETNLE", /* 173 */\r
+ "SETNO", /* 174 */\r
+ "SETNP", /* 175 */\r
+ "SETNS", /* 176 */\r
+ "SETNZ", /* 177 */\r
+ "SETO", /* 178 */\r
+ "SETP", /* 179 */\r
+ "SETPE", /* 180 */\r
+ "SETPO", /* 181 */\r
+ "SETS", /* 182 */\r
+ "SETZ", /* 183 */\r
+ "SGDT", /* 184 */\r
+ "SHL", /* 185 */\r
+ "SHLD", /* 186 */\r
+ "SHR", /* 187 */\r
+ "SHRD", /* 188 */\r
+ "SIDT", /* 189 */\r
+ "SLDT", /* 190 */\r
+ "SMSW", /* 191 */\r
+ "STC", /* 192 */\r
+ "STD", /* 193 */\r
+ "STI", /* 194 */\r
+ "STOS", /* 195 */\r
+ "STOSB", /* 196 */\r
+ "STOSD", /* 197 */\r
+ "STOSW", /* 198 */\r
+ "STR", /* 199 */\r
+ "SUB", /* 200 */\r
+\r
+ "TEST", /* 201 */\r
+\r
+ "VERR", /* 202 */\r
+ "VERW", /* 203 */\r
+\r
+ "WAIT", /* 204 */\r
+ "XCHG", /* 205 */\r
+ "XLAT", /* 206 */\r
+ "XLATB", /* 207 */\r
+ "XOR"}; /* 208 */\r
+\r
+#define xAAA 1\r
+#define xAAD 2\r
+#define xAAM 3\r
+#define xAAS 4\r
+#define xADC 5\r
+#define xADD 6\r
+#define xAND 7\r
+#define xARPL 8\r
+\r
+#define xBOUND 9\r
+#define xBSF 10\r
+#define xBSR 11\r
+#define xBT 12\r
+#define xBTC 13\r
+#define xBTR 14\r
+#define xBTS 15\r
+\r
+#define xCALL 16\r
+#define xCBW 17\r
+#define xCDQ 18\r
+#define xCLC 19\r
+#define xCLD 20\r
+#define xCLI 21\r
+#define xCLTS 22\r
+#define xCMC 23\r
+#define xCMP 24\r
+#define xCMPS 25\r
+#define xCMPSB 26\r
+#define xCMPSD 27\r
+#define xCMPSW 28\r
+#define xCWD 29\r
+#define xCWDE 30\r
+\r
+#define xDAA 31\r
+#define xDAS 32\r
+#define xDEC 33\r
+#define xDIV 34\r
+\r
+#define xENTER 35\r
+#define xHLT 36\r
+\r
+#define xIDIV 37\r
+#define xIMUL 38\r
+#define xIN 39\r
+#define xINC 40\r
+#define xINS 41\r
+#define xINSB 42\r
+#define xINSD 43\r
+#define xINSW 44\r
+#define xINT 45\r
+#define xINTO 46\r
+#define xIRET 47\r
+#define xIRETD 48\r
+\r
+#define xJA 49\r
+#define xJAE 50\r
+#define xJB 51\r
+#define xJBE 52\r
+#define xJC 53\r
+#define xJCXZ 54\r
+#define xJE 55\r
+#define xJECXZ 56\r
+#define xJG 57\r
+#define xJGE 58\r
+#define xJL 59\r
+#define xJLE 60\r
+#define xJMP 61\r
+#define xJNA 62\r
+#define xJNAE 63\r
+#define xJNB 64\r
+#define xJNBE 65\r
+#define xJNC 66\r
+#define xJNE 67\r
+#define xJNG 68\r
+#define xJNGE 69\r
+#define xJNL 70\r
+#define xJNLE 71\r
+#define xJNO 72\r
+#define xJNP 73\r
+#define xJNS 74\r
+#define xJNZ 75\r
+#define xJO 76\r
+#define xJP 77\r
+#define xJPE 78\r
+#define xJPO 79\r
+#define xJS 80\r
+#define xJZ 81\r
+\r
+#define xLAHF 82\r
+#define xLAR 83\r
+#define xLDS 84\r
+#define xLEA 85\r
+#define xLEAVE 86\r
+#define xLES 87\r
+#define xLFS 88\r
+#define xLGDT 89\r
+#define xLGS 90\r
+#define xLIDT 91\r
+#define xLLDT 92\r
+#define xLMSW 93\r
+#define xLOCK 94\r
+#define xLODS 95\r
+#define xLODSB 96\r
+#define xLODSD 97\r
+#define xLODSW 98\r
+#define xLOOP 99\r
+#define xLOOPE 100\r
+#define xLOOPNE 101\r
+#define xLOOPNZ 102\r
+#define xLOOPZ 103\r
+#define xLSL 104\r
+#define xLSS 105\r
+#define xLTR 106\r
+\r
+#define xMOV 107\r
+#define xMOVS 108\r
+#define xMOVSB 109\r
+#define xMOVSD 110\r
+#define xMOVSW 111\r
+#define xMOVSX 112\r
+#define xMOVZX 113\r
+#define xMUL 114\r
+\r
+#define xNEG 115\r
+#define xNOP 116\r
+#define xNOT 117\r
+\r
+#define xOR 118\r
+#define xOUT 119\r
+#define xOUTS 120\r
+#define xOUTSB 121\r
+#define xOUTSD 122\r
+#define xOUTSW 123\r
+\r
+#define xPOP 124\r
+#define xPOPA 125\r
+#define xPOPAD 126\r
+#define xPOPF 127\r
+#define xPOPFD 128\r
+#define xPUSH 129\r
+#define xPUSHA 130\r
+#define xPUSHAD 131\r
+#define xPUSHF 132\r
+#define xPUSHFD 133\r
+\r
+#define xRCL 134\r
+#define xRCR 135\r
+#define xREP 136\r
+#define xREPE 137\r
+#define xREPNE 138\r
+#define xREPNZ 139\r
+#define xREPZ 140\r
+#define xRET 141\r
+#define xRETF 142\r
+#define xRETN 143\r
+#define xROL 144\r
+#define xROR 145\r
+\r
+#define xSAHF 146\r
+#define xSAL 147\r
+#define xSAR 148\r
+#define xSBB 149\r
+#define xSCAS 150\r
+#define xSCASB 151\r
+#define xSCASD 152\r
+#define xSCASW 153\r
+#define xSETA 154\r
+#define xSETAE 155\r
+#define xSETB 156\r
+#define xSETBE 157\r
+#define xSETC 158\r
+#define xSETE 159\r
+#define xSETG 160\r
+#define xSETGE 161\r
+#define xSETL 162\r
+#define xSETLE 163\r
+#define xSETNA 164\r
+#define xSETNAE 165\r
+#define xSETNB 166\r
+#define xSETNBE 167\r
+#define xSETNC 168\r
+#define xSETNE 169\r
+#define xSETNG 170\r
+#define xSETNGE 171\r
+#define xSETNL 172\r
+#define xSETNLE 173\r
+#define xSETNO 174\r
+#define xSETNP 175\r
+#define xSETNS 176\r
+#define xSETNZ 177\r
+#define xSETO 178\r
+#define xSETP 179\r
+#define xSETPE 180\r
+#define xSETPO 181\r
+#define xSETS 182\r
+#define xSETZ 183\r
+#define xSGDT 184\r
+#define xSHL 185\r
+#define xSHLD 186\r
+#define xSHR 187\r
+#define xSHRD 188\r
+#define xSIDT 189\r
+#define xSLDT 190\r
+#define xSMSW 191\r
+#define xSTC 192\r
+#define xSTD 193\r
+#define xSTI 194\r
+#define xSTOS 195\r
+#define xSTOSB 196\r
+#define xSTOSD 197\r
+#define xSTOSW 198\r
+#define xSTR 199\r
+#define xSUB 200\r
+\r
+#define xTEST 201\r
+\r
+#define xVERR 202\r
+#define xVERW 203\r
+\r
+#define xWAIT 204\r
+#define xXCHG 205\r
+#define xXLAT 206\r
+#define xXLATB 207\r
+#define xXOR 208\r
+\r
+\r
+#define nrinst 80 /* number of float instructions */\r
+#define srinst 8\r
+char rgrinst[nrinst][srinst] = { /* 560 bytes */\r
+\r
+ "F2XM1", /* 01 */\r
+ "FABS", /* 02 */\r
+ "FADD", /* 03 */\r
+ "FADDP", /* 04 */\r
+ "FBLD", /* 05 */\r
+ "FBSTP", /* 06 */\r
+ "FCHS", /* 07 */\r
+ "FCLEX", /* 08 */\r
+ "FCOM", /* 09 */\r
+ "FCOMP", /* 10 */\r
+ "FCOMPP", /* 11 */\r
+ "FCOS", /* 12 */\r
+ "FDECSTP", /* 13 */\r
+ "FDIV", /* 14 */\r
+ "FDIVP", /* 15 */\r
+ "FDIVR", /* 16 */\r
+ "FDIVRP", /* 17 */\r
+ "FFREE", /* 18 */\r
+ "FIADD", /* 19 */\r
+ "FICOM", /* 20 */\r
+ "FICOMP", /* 21 */\r
+ "FIDIV", /* 22 */\r
+ "FIDIVR", /* 23 */\r
+ "FILD", /* 24 */\r
+ "FIMUL", /* 25 */\r
+ "FINCSTP", /* 26 */\r
+ "FINIT", /* 27 */\r
+ "FIST", /* 28 */\r
+ "FISTP", /* 29 */\r
+ "FISUB", /* 30 */\r
+ "FISUBR", /* 31 */\r
+ "FLD", /* 32 */\r
+ "FLD1", /* 33 */\r
+ "FLDCW", /* 34 */\r
+ "FLDENV", /* 35 */\r
+ "FLDL2E", /* 36 */\r
+ "FLDL2T", /* 37 */\r
+ "FLDLG2", /* 38 */\r
+ "FLDLN2", /* 39 */\r
+ "FLDPI", /* 40 */\r
+ "FLDZ", /* 41 */\r
+ "FMUL", /* 42 */\r
+ "FMULP", /* 43 */\r
+ "FNCLEX", /* 44 */\r
+ "FNINIT", /* 45 */\r
+ "FNOP", /* 46 */\r
+ "FNSAVE", /* 47 */\r
+ "FNSTCW", /* 48 */\r
+ "FNSTENV", /* 49 */\r
+ "FNSTSW", /* 50 */\r
+ "FPATAN", /* 51 */\r
+ "FPREM", /* 52 */\r
+ "FPREM1", /* 53 */\r
+ "FPTAN", /* 54 */\r
+ "FRNDINT", /* 55 */\r
+ "FRSTOR", /* 56 */\r
+ "FSAVE", /* 57 */\r
+ "FSCALE", /* 58 */\r
+ "FSIN", /* 59 */\r
+ "FSINCOS", /* 60 */\r
+ "FSQRT", /* 61 */\r
+ "FST", /* 62 */\r
+ "FSTCW", /* 63 */\r
+ "FSTENV", /* 64 */\r
+ "FSTP", /* 65 */\r
+ "FSTSW", /* 66 */\r
+ "FSUB", /* 67 */\r
+ "FSUBP", /* 68 */\r
+ "FSUBPR", /* 69 */\r
+ "FSUBR", /* 70 */\r
+ "FTST", /* 71 */\r
+ "FUCOM", /* 72 */\r
+ "FUCOMP", /* 73 */\r
+ "FUCOMPP", /* 74 */\r
+ "FWAIT", /* 75 */\r
+ "FXAM", /* 76 */\r
+ "FXCH", /* 77 */\r
+ "FXTRACT", /* 78 */\r
+ "FYL2X", /* 79 */\r
+ "FYL2XP1" }; /* 80 */\r
+\r
+\r
+/* END OF INSTRUCTIONS */\r
+\r
+/* Allowed Operand types for instruction sequences\r
+ Start numbering at 61 so they don't conflict with\r
+ token values or special characters */\r
+\r
+#define rel8 61 /* mem address within +/-127 bytes of currnt address */\r
+#define relW 62 /* mem address relative (WORD/DWORD) of current addr */\r
+#define iSAD 63 /* immediate segment address (seg16:offset16/32) */\r
+#define r8 64 /* Reg: AL, BL, CL, DL, AH, BH, CH, DH */\r
+#define r16 65 /* Reg: AX, BX, CX, DX, SP, BP, SI, DI */\r
+#define r32 66 /* Reg: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI */\r
+#define rREG 67 /* Any 8, 16 or 32 bit general register */\r
+#define rRGW 68 /* Any 16 or 32 bit general register */\r
+#define rACC 69 /* Reg: Accumulator AL, AX, EAX (any size) */\r
+#define rSEG 70 /* Reg: CS, DS, SS, ES, FS, GS */\r
+#define rCRG 71 /* Reg: CR0, CR2, CR3 */\r
+#define rDRG 72 /* Reg: DR0, DR1, DR2, DR3, DR6, DR7 */\r
+#define rTRG 73 /* Reg: TR6, TR7 */\r
+#define imm8 74 /* Immediate BYTE - UNSIGNED*/\r
+#define ims8 75 /* Immediate BYTE - Will be SIGN Extended!!! */\r
+#define imm16 76 /* Immediate WORD signed value */\r
+#define immX 77 /* immediate size value to match the other operand */\r
+#define rm8 78 /* r8 or memory address to BYTE */\r
+#define rm16 79 /* r16 or memory address to WORD */\r
+#define rRM 80 /* Any 8, 16 or 32 bit register or memory ref */\r
+#define rRMW 81 /* Any 16 or 32 bit register or memory ref */\r
+#define mem 82 /* Memory address. Any legal data mem reference */\r
+#define memF 83 /* Memory address of a 16:32 ptr value */\r
+#define moff 84 /* Memory address (Immediate, Disp only, Seg relative)*/\r
+#define immv3 85 /* immediate value 3 for INT 03 debug */\r
+#define immv1 86 /* immediate value 1 for some instructions (SHL etc.) */\r
+\r
+/* these are only used in the rgMEM32 table */\r
+\r
+#define val8 87 /* Indicates numeric value for displacement, */\r
+#define val16 88 /* immediate, address, etc. Used in memory model */\r
+#define val32 89 /* template. */\r
+\r
+\r
+/* Instruction sequence lookup table is made of:\r
+ - Instruction number (from definitions above)\r
+ - Opr1-3 are the legal operands for the instructions\r
+ - Opc is base opcode.\r
+ - Oprm is the ModR/M byte (if needed). It is partially filled in\r
+ and used as indicated by Om1 below.\r
+ - Opfx - Operand prefix and operand count for instruction.\r
+ qP0F - Prefix Opc with 0x0f\r
+ qUW - Use 0x66 prefix always\r
+ qU16 - If USE16 prefix Opcodes with 0x66.\r
+ qU32 - If USE32 prefix Opcodes with 0x66.\r
+\r
+ - Om1 - Modifications or additions to OpCode to complete instruction:\r
+ zMOP - Use Oprm as ModR/M byte (which is already filled in\r
+ partially with Opcode in bits 3-5). If operand 1 is\r
+ register, placed code in R/M field of ModR/M byte (bits 0-2).\r
+ If operand 1 is mem, handle normally. In special case of\r
+ AAD and AAM instructions Oprm is actually second byte of\r
+ opcode (no operands to handle).\r
+ zMR1 - Use Oprm as ModR/M byte. Register in operand 1\r
+ must be encoded in REG/OPC field of ModR/M. If reg in\r
+ operand 2 it must be incoded in R/M field.\r
+ zMR2 - Use Oprm as ModR/M byte. Register in operand 2\r
+ must be encoded in REG/OPC field of ModR/M. If reg in\r
+ operand 1, it must be encoded in R/M field.\r
+ zORD - OR Opc1 with 01 if WORD or DWORD reg/mem\r
+ zAR1 - No ModRM, Add register code in operand 1 to Opc byte to\r
+ complete the opcode.\r
+ zAR2 - No ModRM, Add register code in operand 2 to Opc byte to\r
+ complete the opcode.\r
+ zRG1 - If register in operand 1, it must be encoded in\r
+ REG/OPC field of ModR/M, else handle memory operand normally.\r
+ zSIZ - This is not actually a modification to the instruction,\r
+ but tells the assembler that the operand sizes will not\r
+ match and that it's ok. The operand size should be the\r
+ size of the first operand.\r
+\r
+ */\r
+\r
+/* Prefix instruction/operand count byte */\r
+\r
+#define qP0F 0x01\r
+#define qU16 0x02\r
+#define qU32 0x04\r
+#define qUW 0x08\r
+\r
+/* OM1 instruction byte (Opcode Modifier/Special build instructions) */\r
+#define zMOP 0x01\r
+#define zMR1 0x02\r
+#define zMR2 0x04\r
+#define zORD 0x08\r
+#define zAR1 0x10\r
+#define zAR2 0x20\r
+#define zRG1 0x40\r
+#define zSIZ 0x80\r
+\r
+\r
+/* Certain table entries were added for optimization to ensure that\r
+ the shortest instruction is used in all cases. This adds about\r
+ 50 lines to the table, but it's well worth the overhead!\r
+*/\r
+\r
+#define nrgINS 338\r
+unsigned char rgINS[nrgINS][8] = { /* 338 * 8 = */\r
+\r
+/*Inst Opr1 Opr2 Opr3 Opfx Opc Oprm Om1 */\r
+\r
+{0 , 0, 0, 0, 0, 0, 0, 0 },\r
+{xAAA , 0, 0, 0, 0, 0x37, 0, 0 },\r
+{xAAD , 0, 0, 0, 0, 0xd5, 0x0A, zMOP },\r
+{xAAM , 0, 0, 0, 0, 0xd4, 0x0A, zMOP },\r
+{xADC , rACC, immX, 0, 0, 0x14, 0, zORD },\r
+{xADC , rRMW, imm8, 0, 0, 0x83, 0x10, zMOP },\r
+{xADC , rRM, immX, 0, 0, 0x80, 0x10, zMOP|zORD },\r
+{xADC , rRM, rREG, 0, 0, 0x10, 0, zMR2|zORD },\r
+{xADC , rREG, rRM, 0, 0, 0x12, 0, zMR1|zORD },\r
+\r
+{xADD , rRMW, ims8, 0, 0, 0x83, 0, zMOP },\r
+{xADD , rACC, immX, 0, 0, 0x04, 0, zORD },\r
+{xADD , rRM, immX, 0, 0, 0x80, 0, zMOP|zORD },\r
+{xADD , rREG, rRM, 0, 0, 0x02, 0, zMR1|zORD },\r
+{xADD , rRM, rREG, 0, 0, 0x00, 0, zMR2|zORD },\r
+\r
+{xAND , rRMW, ims8, 0, 0, 0x83, 0x20, zMOP },\r
+{xAND , rACC, immX, 0, 0, 0x24, 0, zORD },\r
+{xAND , rRM, immX, 0, 0, 0x80, 0x20, zMOP|zORD },\r
+{xAND , rREG, rRM, 0, 0, 0x22, 0, zMR1|zORD },\r
+{xAND , rRM, rREG, 0, 0, 0x20, 0, zMR2|zORD },\r
+\r
+{xARPL , rm16, r16, 0, 0, 0x63, 0, zMR2 },\r
+{xBOUND , rRMW, mem, 0, 0, 0x62, 0, zMR1 },\r
+{xBSF , rRGW, rRMW, 0, qP0F, 0xbc, 0, zMR1 },\r
+{xBSR , rRGW, rRMW, 0, qP0F, 0xbd, 0, zMR1 },\r
+{xBT , rRMW, rRGW, 0, qP0F, 0xa3, 0, zMR2 },\r
+{xBT , rRMW, imm8, 0, qP0F, 0xba, 0x20, zMOP },\r
+{xBTC , rRMW, rRGW, 0, qP0F, 0xbb, 0, zMR2 },\r
+{xBTC , rRMW, imm8, 0, qP0F, 0xba, 0x38, zMOP },\r
+{xBTR , rRMW, rRGW, 0, qP0F, 0xb3, 0, zMR2 },\r
+{xBTR , rRMW, imm8, 0, qP0F, 0xba, 0x30, zMOP },\r
+{xBTS , rRMW, rRGW, 0, qP0F, 0xab, 0, zMR2 },\r
+{xBTS , rRMW, imm8, 0, qP0F, 0xba, 0x28, zMOP },\r
+{xCALL , relW, 0, 0, 0, 0xe8, 0, 0 },\r
+{xCALL , rRMW, 0, 0, 0, 0xff, 0x10, zMOP },\r
+{xCALL , iSAD, 0, 0, 0, 0x9a, 0, 0 },\r
+{xCALL , memF, 0, 0, 0, 0xff, 0x18, zMOP },\r
+{xCBW , 0, 0, 0, qU32, 0x98, 0, 0 },\r
+{xCWDE , 0, 0, 0, qU16, 0x98, 0, 0 },\r
+{xCLC , 0, 0, 0, 0, 0xf8, 0, 0 },\r
+{xCLD , 0, 0, 0, 0, 0xfc, 0, 0 },\r
+{xCLI , 0, 0, 0, 0, 0xfa, 0, 0 },\r
+{xCLTS , 0, 0, 0, qP0F, 0x06, 0, 0 },\r
+{xCMC , 0, 0, 0, 0, 0xf5, 0, 0 },\r
+\r
+{xCMP , rRMW, ims8, 0, 0, 0x83, 0x38, zMOP },\r
+{xCMP , rACC, immX, 0, 0, 0x3c, 0, zORD },\r
+{xCMP , rRM, immX, 0, 0, 0x80, 0x38, zMOP|zORD },\r
+{xCMP , rREG, rRM, 0, 0, 0x3a, 0, zMR1|zORD },\r
+{xCMP , rRM, rREG, 0, 0, 0x38, 0, zMR2|zORD },\r
+\r
+{xCMPSB , 0, 0, 0, 0, 0xa6, 0, 0 },\r
+{xCMPSD , 0, 0, 0, 0, 0xa7, 0, 0 },\r
+{xCMPSW , 0, 0, 0, qUW, 0xa7, 0, 0 },\r
+{xCWD , 0, 0, 0, qUW, 0x99, 0, 0 },\r
+{xCDQ , 0, 0, 0, qU16, 0x99, 0, 0 },\r
+{xDAA , 0, 0, 0, 0, 0x27, 0, 0 },\r
+{xDAS , 0, 0, 0, 0, 0x2f, 0, 0 },\r
+{xDEC , rRGW, 0, 0, 0, 0x48, 0, zAR1 },\r
+{xDEC , rRM, 0, 0, 0, 0xfe, 0x08, zMOP|zORD },\r
+{xDIV , rRM, 0, 0, 0, 0xf6, 0x30, zMOP|zORD },\r
+{xENTER , imm16, imm8, 0, 0, 0xc8, 0, zSIZ },\r
+{xHLT , 0, 0, 0, 0, 0xf4, 0, 0 },\r
+{xIDIV , rRM, 0, 0, 0, 0xf6, 0x38, zMOP|zORD },\r
+{xIMUL , rRM, 0, 0, 0, 0xf6, 0x28, zMOP|zORD },\r
+{xIMUL , rRGW, rRMW, 0, qP0F, 0xaf, 0, zMR1 },\r
+{xIMUL , rRGW, rRMW, imm8, 0, 0x6b, 0, zMR1 },\r
+{xIMUL , rRGW, imm8, 0, 0, 0x6b, 0, zMR1|zSIZ },\r
+{xIMUL , rRGW, rRMW, immX, 0, 0x69, 0, zMR1 },\r
+{xIMUL , rRGW, immX, 0, 0, 0x69, 0, zMR1 },\r
+{xIN , rACC, imm8, 0, 0, 0xe4, 0, zORD|zSIZ },\r
+{xIN , rACC, rDX, 0, 0, 0xec, 0, zORD|zSIZ },\r
+{xINC , rRGW, 0, 0, 0, 0x40, 0, zAR1 },\r
+{xINC , rRM, 0, 0, 0, 0xfe, 0, zMOP|zORD },\r
+{xINSB , 0, 0, 0, 0, 0x6C, 0, 0 },\r
+{xINSD , 0, 0, 0, 0, 0x6D, 0, 0 },\r
+{xINSW , 0, 0, 0, qUW, 0x6D, 0, 0 },\r
+{xINT , immv3, 0, 0, 0, 0xcc, 0, 0 },\r
+{xINT , imm8, 0, 0, 0, 0xcd, 0, 0 },\r
+{xINTO , 0, 0, 0, 0, 0xce, 0, 0 },\r
+{xIRET , 0, 0, 0, qUW, 0xcf, 0, 0 },\r
+{xIRETD , 0, 0, 0, 0, 0xcf, 0, 0 },\r
+{xJA , rel8, 0, 0, 0, 0x77, 0, 0 },\r
+{xJA , relW, 0, 0, qP0F, 0x87, 0, 0 },\r
+{xJAE , rel8, 0, 0, 0, 0x73, 0, 0 },\r
+{xJAE , relW, 0, 0, qP0F, 0x83, 0, 0 },\r
+{xJB , rel8, 0, 0, 0, 0x72, 0, 0 },\r
+{xJB , relW, 0, 0, qP0F, 0x82, 0, 0 },\r
+{xJBE , rel8, 0, 0, 0, 0x76, 0, 0 },\r
+{xJBE , relW, 0, 0, qP0F, 0x86, 0, 0 },\r
+{xJC , rel8, 0, 0, 0, 0x72, 0, 0 },\r
+{xJC , relW, 0, 0, qP0F, 0x82, 0, 0 },\r
+{xJCXZ , rel8, 0, 0, 0, 0xe3, 0, 0 },\r
+{xJNBE , rel8, 0, 0, 0, 0x77, 0, 0 },\r
+{xJNBE , relW, 0, 0, qP0F, 0x87, 0, 0 },\r
+{xJNB , rel8, 0, 0, 0, 0x73, 0, 0 },\r
+{xJNB , relW, 0, 0, qP0F, 0x83, 0, 0 },\r
+{xJNC , rel8, 0, 0, 0, 0x73, 0, 0 },\r
+{xJNC , relW, 0, 0, qP0F, 0x83, 0, 0 },\r
+{xJNA , rel8, 0, 0, 0, 0x76, 0, 0 },\r
+{xJNA , relW, 0, 0, qP0F, 0x86, 0, 0 },\r
+{xJNAE , rel8, 0, 0, 0, 0x72, 0, 0 },\r
+{xJNAE , relW, 0, 0, qP0F, 0x82, 0, 0 },\r
+{xJECXZ , rel8, 0, 0, 0, 0xe3, 0, 0 },\r
+{xJE , rel8, 0, 0, 0, 0x74, 0, 0 },\r
+{xJE , relW, 0, 0, qP0F, 0x84, 0, 0 },\r
+{xJG , rel8, 0, 0, 0, 0x7f, 0, 0 },\r
+{xJG , relW, 0, 0, qP0F, 0x8f, 0, 0 },\r
+{xJGE , rel8, 0, 0, 0, 0x7d, 0, 0 },\r
+{xJGE , relW, 0, 0, qP0F, 0x8d, 0, 0 },\r
+{xJNL , rel8, 0, 0, 0, 0x7d, 0, 0 },\r
+{xJNL , relW, 0, 0, qP0F, 0x8d, 0, 0 },\r
+{xJL , rel8, 0, 0, 0, 0x7c, 0, 0 },\r
+{xJL , relW, 0, 0, qP0F, 0x8c, 0, 0 },\r
+{xJNGE , rel8, 0, 0, 0, 0x7c, 0, 0 },\r
+{xJNGE , relW, 0, 0, qP0F, 0x8c, 0, 0 },\r
+{xJLE , rel8, 0, 0, 0, 0x7e, 0, 0 },\r
+{xJLE , relW, 0, 0, qP0F, 0x8e, 0, 0 },\r
+{xJNG , rel8, 0, 0, 0, 0x7e, 0, 0 },\r
+{xJNG , relW, 0, 0, qP0F, 0x8e, 0, 0 },\r
+{xJNE , rel8, 0, 0, 0, 0x75, 0, 0 },\r
+{xJNE , relW, 0, 0, qP0F, 0x85, 0, 0 },\r
+{xJNLE , rel8, 0, 0, 0, 0x7f, 0, 0 },\r
+{xJNLE , relW, 0, 0, qP0F, 0x8f, 0, 0 },\r
+{xJNO , rel8, 0, 0, 0, 0x71, 0, 0 },\r
+{xJNO , relW, 0, 0, qP0F, 0x81, 0, 0 },\r
+{xJNP , rel8, 0, 0, 0, 0x7b, 0, 0 },\r
+{xJNP , relW, 0, 0, qP0F, 0x8b, 0, 0 },\r
+{xJNS , rel8, 0, 0, 0, 0x79, 0, 0 },\r
+{xJNS , relW, 0, 0, qP0F, 0x89, 0, 0 },\r
+{xJNZ , rel8, 0, 0, 0, 0x75, 0, 0 },\r
+{xJNZ , relW, 0, 0, qP0F, 0x85, 0, 0 },\r
+{xJO , rel8, 0, 0, 0, 0x70, 0, 0 },\r
+{xJO , relW, 0, 0, qP0F, 0x80, 0, 0 },\r
+{xJP , rel8, 0, 0, 0, 0x7a, 0, 0 },\r
+{xJP , relW, 0, 0, qP0F, 0x8a, 0, 0 },\r
+{xJPO , rel8, 0, 0, 0, 0x7b, 0, 0 },\r
+{xJPO , relW, 0, 0, qP0F, 0x8b, 0, 0 },\r
+{xJPE , rel8, 0, 0, 0, 0x7a, 0, 0 },\r
+{xJPE , relW, 0, 0, qP0F, 0x8a, 0, 0 },\r
+{xJS , rel8, 0, 0, 0, 0x78, 0, 0 },\r
+{xJS , relW, 0, 0, qP0F, 0x88, 0, 0 },\r
+{xJZ , rel8, 0, 0, 0, 0x74, 0, 0 },\r
+{xJZ , relW, 0, 0, qP0F, 0x84, 0, 0 },\r
+{xJMP , rel8, 0, 0, 0, 0xeb, 0, 0 },\r
+{xJMP , relW, 0, 0, 0, 0xe9, 0, 0 },\r
+{xJMP , rRMW, 0, 0, 0, 0xff, 0x20, zMOP },\r
+{xJMP , iSAD, 0, 0, 0, 0xea, 0, 0 },\r
+{xJMP , memF, 0, 0, 0, 0xff, 0x28, zMOP },\r
+{xLAHF , 0, 0, 0, 0, 0x9f, 0, 0 },\r
+{xLAR , rRGW, rRMW, 0, qP0F, 0x02, 0, zMR1 },\r
+{xLEA , rRGW, mem, 0, 0, 0x8d, 0, zMR1|zSIZ },\r
+{xLEAVE , 0, 0, 0, 0, 0xc9, 0, 0 },\r
+{xLGDT , memF, 0, 0, qP0F, 0x01, 0x10, zMOP },\r
+{xLIDT , memF, 0, 0, qP0F, 0x01, 0x18, zMOP },\r
+{xLDS , rRGW, memF, 0, 0, 0xc5, 0, zMR1 },\r
+{xLSS , rRGW, memF, 0, qP0F, 0xb2, 0, zMR1 },\r
+{xLES , rRGW, memF, 0, 0, 0xc4, 0, zMR1 },\r
+{xLFS , rRGW, memF, 0, qP0F, 0xb4, 0, zMR1 },\r
+{xLGS , rRGW, memF, 0, qP0F, 0xb5, 0, zMR1 },\r
+{xLLDT , rm16, 0, 0, qP0F, 0x00, 0x10, zMOP },\r
+{xLMSW , rm16, 0, 0, qP0F, 0x01, 0x30, zMOP },\r
+{xLOCK , 0, 0, 0, 0, 0xf0, 0, 0 },\r
+{xLODSB , 0, 0, 0, 0, 0xac, 0, 0 },\r
+{xLODSD , 0, 0, 0, 0, 0xad, 0, 0 },\r
+{xLODSW , 0, 0, 0, qUW, 0xad, 0, 0 },\r
+{xLOOP , rel8, 0, 0, 0, 0xe2, 0, 0 },\r
+{xLOOPE , rel8, 0, 0, 0, 0xe1, 0, 0 },\r
+{xLOOPZ , rel8, 0, 0, 0, 0xe1, 0, 0 },\r
+{xLOOPNE, rel8, 0, 0, 0, 0xe0, 0, 0 },\r
+{xLOOPNZ, rel8, 0, 0, 0, 0xe0, 0, 0 },\r
+{xLSL , rRGW, rRMW, 0, qP0F, 0x03, 0, zMR1 },\r
+{xLTR , rm16, 0, 0, qP0F, 0x00, 0x18, zMOP },\r
+{xMOV , rACC, moff, 0, 0, 0xA0, 0, zORD },\r
+{xMOV , moff, rACC, 0, 0, 0xA2, 0, zORD },\r
+{xMOV , r8, imm8, 0, 0, 0xb0, 0, zAR1 },\r
+{xMOV , rRGW, immX, 0, 0, 0xb8, 0, zAR1 },\r
+{xMOV , rREG, rRM, 0, 0, 0x8a, 0, zMR1|zORD },\r
+{xMOV , rRM, rREG, 0, 0, 0x88, 0, zMR2|zORD },\r
+{xMOV , rRM, immX, 0, 0, 0xc6, 0, zMR1|zORD },/*?*/\r
+{xMOV , rm16, rSEG, 0, 0, 0x8c, 0, zMR2 },\r
+{xMOV , rSEG, rm16, 0, 0, 0x8e, 0, zMR1 },\r
+{xMOV , r32, rCRG, 0, qP0F, 0x20, 0, zMR2 },\r
+{xMOV , rCRG, r32, 0, qP0F, 0x22, 0, zMR1 },\r
+{xMOV , r32, rDRG, 0, qP0F, 0x21, 0, zMR2 },\r
+{xMOV , rDRG, r32, 0, qP0F, 0x23, 0, zMR1 },\r
+{xMOV , r32, rTRG, 0, qP0F, 0x24, 0, zMR2 },\r
+{xMOV , rTRG, r32, 0, qP0F, 0x26, 0, zMR1 },\r
+{xMOVSB , 0, 0, 0, 0, 0xa4, 0, 0 },\r
+{xMOVSD , 0, 0, 0, 0, 0xa5, 0, 0 },\r
+{xMOVSW , 0, 0, 0, qUW, 0xa5, 0, 0 },\r
+{xMOVSX , r32, rm16, 0, qP0F, 0xbf, 0, zMR1|zSIZ },\r
+{xMOVSX , rRGW, rm8, 0, qP0F, 0xbe, 0, zMR1|zSIZ },\r
+{xMOVZX , r32, rm16, 0, qP0F, 0xb7, 0, zMR1|zSIZ },\r
+{xMOVZX , rRGW, rm8, 0, qP0F, 0xb6, 0, zMR1|zSIZ },\r
+{xMUL , rRM, 0, 0, 0, 0xf6, 0x20, zMOP|zORD },\r
+{xNEG , rRM, 0, 0, 0, 0xf6, 0x18, zMOP|zORD },\r
+{xNOP , 0, 0, 0, 0, 0x90, 0, 0 },\r
+{xNOT , rRM, 0, 0, 0, 0xf6, 0x10, zMOP|zORD },\r
+\r
+{xOR , rRMW, ims8, 0, 0, 0x83, 0x08, zMOP },\r
+{xOR , rACC, immX, 0, 0, 0x0c, 0, zORD },\r
+{xOR , rRM, immX, 0, 0, 0x80, 0x08, zMOP|zORD },\r
+{xOR , rREG, rRM, 0, 0, 0x0a, 0, zMR1|zORD },\r
+{xOR , rRM, rREG, 0, 0, 0x08, 0, zMR2|zORD },\r
+\r
+{xOUT , imm8, rACC, 0, 0, 0xe6, 0, zORD },\r
+{xOUT , rDX, rACC, 0, 0, 0xee, 0, zORD },\r
+{xOUTSB , 0, 0, 0, 0, 0x6e, 0, 0 },\r
+{xOUTSD , 0, 0, 0, 0, 0x6f, 0, 0 },\r
+{xOUTSW , 0, 0, 0, qUW, 0x6f, 0, 0 },\r
+{xPOP , mem, 0, 0, 0, 0x8f, 0, zMOP },\r
+{xPOP , rRGW, 0, 0, 0, 0x58, 0, zAR1 },\r
+{xPOP , rDS, 0, 0, 0, 0x1f, 0, 0 },\r
+{xPOP , rES, 0, 0, 0, 0x07, 0, 0 },\r
+{xPOP , rSS, 0, 0, 0, 0x17, 0, 0 },\r
+{xPOP , rFS, 0, 0, qP0F, 0xa1, 0, 0 },\r
+{xPOP , rGS, 0, 0, qP0F, 0xa9, 0, 0 },\r
+{xPOPA , 0, 0, 0, 0, 0x61, 0, 0 },\r
+{xPOPAD , 0, 0, 0, 0, 0x61, 0, 0 },\r
+{xPOPF , 0, 0, 0, 0, 0x9d, 0, 0 },\r
+{xPOPFD , 0, 0, 0, 0, 0x9d, 0, 0 },\r
+{xPUSH , mem, 0, 0, 0, 0xff, 0x30, zMOP },\r
+{xPUSH , rRGW, 0, 0, 0, 0x50, 0, zAR1 },\r
+{xPUSH , ims8, 0, 0, 0, 0x6a, 0, 0 },\r
+{xPUSH , immX, 0, 0, 0, 0x68, 0, 0 },\r
+{xPUSH , rCS, 0, 0, 0, 0x0e, 0, 0 },\r
+{xPUSH , rSS, 0, 0, 0, 0x16, 0, 0 },\r
+{xPUSH , rDS, 0, 0, 0, 0x1e, 0, 0 },\r
+{xPUSH , rES, 0, 0, 0, 0x06, 0, 0 },\r
+{xPUSH , rFS, 0, 0, qP0F, 0xa0, 0, 0 },\r
+{xPUSH , rGS, 0, 0, qP0F, 0xa8, 0, 0 },\r
+{xPUSHA , 0, 0, 0, 0, 0x60, 0, 0 },\r
+{xPUSHAD, 0, 0, 0, 0, 0x60, 0, 0 },\r
+{xPUSHF , 0, 0, 0, 0, 0x9c, 0, 0 },\r
+{xPUSHFD, 0, 0, 0, 0, 0x9c, 0, 0 },\r
+{xRCL , rRM, immv1, 0, 0, 0xd0, 0x10, zMOP|zORD|zSIZ },\r
+{xRCL , rRM, rCL, 0, 0, 0xd2, 0x10, zMOP|zORD|zSIZ },\r
+{xRCL , rRM, imm8, 0, 0, 0xc0, 0x10, zMOP|zORD|zSIZ },\r
+{xRCR , rRM, immv1, 0, 0, 0xd0, 0x18, zMOP|zORD|zSIZ },\r
+{xRCR , rRM, rCL, 0, 0, 0xd2, 0x18, zMOP|zORD|zSIZ },\r
+{xRCR , rRM, imm8, 0, 0, 0xc0, 0x18, zMOP|zORD|zSIZ },\r
+{xROL , rRM, immv1, 0, 0, 0xd0, 0, zMOP|zORD|zSIZ },\r
+{xROL , rRM, rCL, 0, 0, 0xd2, 0, zMOP|zORD|zSIZ },\r
+{xROL , rRM, imm8, 0, 0, 0xc0, 0, zMOP|zORD|zSIZ },\r
+{xROR , rRM, immv1, 0, 0, 0xd0, 0x08, zMOP|zORD|zSIZ },\r
+{xROR , rRM, rCL, 0, 0, 0xd2, 0x08, zMOP|zORD|zSIZ },\r
+{xROR , rRM, imm8, 0, 0, 0xc0, 0x08, zMOP|zORD|zSIZ },\r
+{xREP , 0, 0, 0, 0, 0xf3, 0, 0 },\r
+{xREPE , 0, 0, 0, 0, 0xf3, 0, 0 },\r
+{xREPNE , 0, 0, 0, 0, 0xf2, 0, 0 },\r
+{xRETN , 0, 0, 0, 0, 0xc3, 0, 0 },\r
+{xRETN , imm16, 0, 0, 0, 0xc2, 0, 0 },\r
+{xRETF , 0, 0, 0, 0, 0xcb, 0, 0 },\r
+{xRETF , imm16, 0, 0, 0, 0xca, 0, 0 },\r
+{xSAL , rRM, immv1, 0, 0, 0xd0, 0x20, zMOP|zORD|zSIZ },\r
+{xSAL , rRM, rCL, 0, 0, 0xd2, 0x20, zMOP|zORD|zSIZ },\r
+{xSAL , rRM, imm8, 0, 0, 0xc0, 0x20, zMOP|zORD|zSIZ },\r
+{xSAR , rRM, immv1, 0, 0, 0xd0, 0x38, zMOP|zORD|zSIZ },\r
+{xSAR , rRM, rCL, 0, 0, 0xd2, 0x38, zMOP|zORD|zSIZ },\r
+{xSAR , rRM, imm8, 0, 0, 0xc0, 0x38, zMOP|zORD|zSIZ },\r
+{xSHL , rRM, immv1, 0, 0, 0xd0, 0x20, zMOP|zORD|zSIZ },\r
+{xSHL , rRM, rCL, 0, 0, 0xd2, 0x20, zMOP|zORD|zSIZ },\r
+{xSHL , rRM, imm8, 0, 0, 0xc0, 0x20, zMOP|zORD|zSIZ },\r
+{xSHR , rRM, immv1, 0, 0, 0xd0, 0x28, zMOP|zORD|zSIZ },\r
+{xSHR , rRM, rCL, 0, 0, 0xd2, 0x28, zMOP|zORD|zSIZ },\r
+{xSHR , rRM, imm8, 0, 0, 0xc0, 0x28, zMOP|zORD|zSIZ },\r
+\r
+{xSBB , rRMW, ims8, 0, 0, 0x83, 0x18, zMOP },\r
+{xSBB , rACC, immX, 0, 0, 0x1c, 0, zORD },\r
+{xSBB , rRM, immX, 0, 0, 0x80, 0x18, zMOP|zORD },\r
+{xSBB , rREG, rRM, 0, 0, 0x1a, 0, zMR1|zORD },\r
+{xSBB , rRM, rREG, 0, 0, 0x18, 0, zMR2|zORD },\r
+\r
+{xSCASB , 0, 0, 0, 0, 0xae, 0, 0 },\r
+{xSCASD , 0, 0, 0, 0, 0xaf, 0, 0 },\r
+{xSCASW , 0, 0, 0, qUW, 0xaf, 0, 0 },\r
+{xSETA , rm8, 0, 0, qP0F, 0x97, 0, zRG1 },\r
+{xSETAE , rm8, 0, 0, qP0F, 0x93, 0, zRG1 },\r
+{xSETB , rm8, 0, 0, qP0F, 0x92, 0, zRG1 },\r
+{xSETBE , rm8, 0, 0, qP0F, 0x96, 0, zRG1 },\r
+{xSETC , rm8, 0, 0, qP0F, 0x92, 0, zRG1 },\r
+{xSETE , rm8, 0, 0, qP0F, 0x94, 0, zRG1 },\r
+{xSETG , rm8, 0, 0, qP0F, 0x9F, 0, zRG1 },\r
+{xSETGE , rm8, 0, 0, qP0F, 0x9D, 0, zRG1 },\r
+{xSETL , rm8, 0, 0, qP0F, 0x9C, 0, zRG1 },\r
+{xSETLE , rm8, 0, 0, qP0F, 0x9E, 0, zRG1 },\r
+{xSETNA , rm8, 0, 0, qP0F, 0x96, 0, zRG1 },\r
+{xSETNAE, rm8, 0, 0, qP0F, 0x92, 0, zRG1 },\r
+{xSETNB , rm8, 0, 0, qP0F, 0x93, 0, zRG1 },\r
+{xSETNBE, rm8, 0, 0, qP0F, 0x97, 0, zRG1 },\r
+{xSETNC , rm8, 0, 0, qP0F, 0x93, 0, zRG1 },\r
+{xSETNE , rm8, 0, 0, qP0F, 0x95, 0, zRG1 },\r
+{xSETNG , rm8, 0, 0, qP0F, 0x9E, 0, zRG1 },\r
+{xSETNGE, rm8, 0, 0, qP0F, 0x9C, 0, zRG1 },\r
+{xSETNL , rm8, 0, 0, qP0F, 0x9D, 0, zRG1 },\r
+{xSETNLE, rm8, 0, 0, qP0F, 0x9F, 0, zRG1 },\r
+{xSETNO , rm8, 0, 0, qP0F, 0x91, 0, zRG1 },\r
+{xSETNP , rm8, 0, 0, qP0F, 0x9B, 0, zRG1 },\r
+{xSETNS , rm8, 0, 0, qP0F, 0x99, 0, zRG1 },\r
+{xSETNZ , rm8, 0, 0, qP0F, 0x95, 0, zRG1 },\r
+{xSETO , rm8, 0, 0, qP0F, 0x90, 0, zRG1 },\r
+{xSETP , rm8, 0, 0, qP0F, 0x9A, 0, zRG1 },\r
+{xSETPE , rm8, 0, 0, qP0F, 0x9A, 0, zRG1 },\r
+{xSETPO , rm8, 0, 0, qP0F, 0x9B, 0, zRG1 },\r
+{xSETS , rm8, 0, 0, qP0F, 0x98, 0, zRG1 },\r
+{xSETZ , rm8, 0, 0, qP0F, 0x94, 0, zRG1 },\r
+{xSGDT , memF, 0, 0, qP0F, 0x01, 0, zMOP },\r
+{xSIDT , memF, 0, 0, qP0F, 0x01, 0x08, zMOP },\r
+{xSHLD , rRMW, rRGW, imm8, qP0F, 0xa4, 0, 0 },\r
+{xSHLD , rRMW, rRGW, rCL, qP0F, 0xa5, 0, 0 },\r
+{xSHRD , rRMW, rRGW, imm8, qP0F, 0xac, 0, 0 },\r
+{xSHRD , rRMW, rRGW, rCL, qP0F, 0xad, 0, 0 },\r
+{xSLDT , rm16, 0, 0, qP0F, 0x00, 0, zMOP },\r
+{xSMSW , rm16, 0, 0, qP0F, 0x01, 0x20, zMOP },\r
+{xSTC , 0, 0, 0, 0, 0xf9, 0, 0 },\r
+{xSTI , 0, 0, 0, 0, 0xfb, 0, 0 },\r
+{xSTD , 0, 0, 0, 0, 0xfd, 0, 0 },\r
+{xSTOSB , 0, 0, 0, 0, 0xaa, 0, 0 },\r
+{xSTOSD , 0, 0, 0, 0, 0xab, 0, 0 },\r
+{xSTOSW , 0, 0, 0, qUW, 0xab, 0, 0 },\r
+{xSTR , rm16, 0, 0, qP0F, 0x00, 0x08, zMOP },\r
+\r
+{xSUB , rRMW, ims8, 0, 0, 0x83, 0x28, zMOP },\r
+{xSUB , rACC, immX, 0, 0, 0x2c, 0, zORD },\r
+{xSUB , rRM, immX, 0, 0, 0x80, 0x28, zMOP|zORD },\r
+{xSUB , rREG, rRM, 0, 0, 0x2a, 0, zMR1|zORD },\r
+{xSUB , rRM, rREG, 0, 0, 0x28, 0, zMR2|zORD },\r
+\r
+{xTEST , rACC, immX, 0, 0, 0xa8, 0, zORD },\r
+{xTEST , rRM, immX, 0, 0, 0xf6, 0, zMOP|zORD },\r
+{xTEST , rREG, rRM, 0, 0, 0x84, 0, zMR1|zORD },\r
+{xVERR , rm16, 0, 0, qP0F, 0x00, 0x20, zMOP },\r
+{xVERW , rm16, 0, 0, qP0F, 0x00, 0x28, zMOP },\r
+{xWAIT , 0, 0, 0, 0, 0x9b, 0, 0 },\r
+{xXCHG , r16, rAX, 0, 0, 0x90, 0, zAR1 },\r
+{xXCHG , rAX, r16, 0, 0, 0x90, 0, zAR2 },\r
+{xXCHG , r32, rEAX, 0, 0, 0x90, 0, zAR1 },\r
+{xXCHG , rEAX, r32, 0, 0, 0x90, 0, zAR2 },\r
+{xXCHG , rRM, rREG, 0, 0, 0x86, 0, zMR2|zORD },\r
+{xXCHG , rREG, rRM, 0, 0, 0x86, 0, zMR1|zORD },\r
+{xXLAT , mem, 0, 0, 0, 0x00, 0, 0 },\r
+{xXLATB , 0, 0, 0, 0, 0x00, 0, 0 },\r
+\r
+{xXOR , rRMW, ims8, 0, 0, 0x83, 0x30, zMOP },\r
+{xXOR , rACC, immX, 0, 0, 0x34, 0, zORD },\r
+{xXOR , rRM, immX, 0, 0, 0x80, 0x30, zMOP|zORD },\r
+{xXOR , rREG, rRM, 0, 0, 0x32, 0, zMR1|zORD },\r
+{xXOR , rRM, rREG, 0, 0, 0x30, 0, zMR2|zORD },\r
+};\r
+\r
+/* END of instruction sequence definitions */\r
+\r
+/* This table provides look-up instructions on building the ModR/M and\r
+ SIB bytes (optional) for all memory references.\r
+ THIS IS ONLY FOR MEMORY REFERENCES.\r
+ The Mod value in this table can be ORed to the ModR/M byte\r
+ and SS value in this table can be ORed to the SIB byte\r
+ for the instruction you're building.\r
+*/\r
+\r
+\r
+#define fBase 0x01\r
+#define fIndx 0x02 /* fScale = 1 by default when fIndx is present */\r
+#define fScale2 0x04\r
+#define fScale4 0x08\r
+#define fScale8 0x10\r
+#define fDisp8 0x20\r
+#define fDisp32 0x40\r
+\r
+#define UseSIB 1\r
+#define nrgM32 20\r
+\r
+U8 rgM32[20][4] = {\r
+/* UseSIB Mod SS */\r
+{ 0, 0, 0x00, 0x00 },\r
+{ fBase, 0, 0x00, 0x00 },\r
+{ fBase | fIndx, 1, 0x04, 0x00 },\r
+{ fIndx | fScale2, 1, 0x04, 0x40 },\r
+{ fIndx | fScale4, 1, 0x04, 0x80 },\r
+{ fIndx | fScale8, 1, 0x04, 0xC0 },\r
+{ fDisp32, 0, 0x05, 0x00 },\r
+{ fBase | fIndx | fScale2, 1, 0x04, 0x40 },\r
+{ fBase | fIndx | fScale4, 1, 0x04, 0x80 },\r
+{ fBase | fIndx | fScale8, 1, 0x04, 0xC0 },\r
+{ fBase | fDisp8, 0, 0x40, 0x00 },\r
+{ fBase | fDisp32, 0, 0x80, 0x00 },\r
+{ fBase | fIndx | fDisp8, 1, 0x44, 0x00 },\r
+{ fBase | fIndx | fDisp32, 1, 0x84, 0x00 },\r
+{ fBase | fIndx | fScale2 | fDisp8, 1, 0x44, 0x40 },\r
+{ fBase | fIndx | fScale4 | fDisp8, 1, 0x44, 0x80 },\r
+{ fBase | fIndx | fScale8 | fDisp8, 1, 0x44, 0xC0 },\r
+{ fBase | fIndx | fScale2 | fDisp32, 1, 0x84, 0x40 },\r
+{ fBase | fIndx | fScale4 | fDisp32, 1, 0x84, 0x80 },\r
+{ fBase | fIndx | fScale8 | fDisp32, 1, 0x84, 0xC0 },\r
+};\r
+\r
+\r
+/* The following 16 bit addressing modes are recognized: */\r
+/* UseSIB is always 0 in 16 bit addressing modes */\r
+\r
+#define nrgM16 24\r
+\r
+int rgM16[24][8] = {\r
+\r
+/* UseSIB Mod SS */\r
+ {rBX, rSI, 0, 0, 0, 0, 0, 0},\r
+ {rBX, rDI, 0, 0, 0, 0, 0, 0},\r
+ {rBP, rSI, 0, 0, 0, 0, 0, 0},\r
+ {rBP, rDI, 0, 0, 0, 0, 0, 0},\r
+ {rSI, 0, 0, 0, 0, 0, 0, 0},\r
+ {rDI, 0, 0, 0, 0, 0, 0, 0},\r
+ {val16, 0, 0, 0, 0, 0, 0, 0},\r
+ {rBX, 0, 0, 0, 0, 0, 0, 0},\r
+ {rBX, rSI, val8, 0, 0, 0, 0, 0},\r
+ {rBX, rDI, val8, 0, 0, 0, 0, 0},\r
+ {rBP, rSI, val8, 0, 0, 0, 0, 0},\r
+ {rBP, rDI, val8, 0, 0, 0, 0, 0},\r
+ {rSI, val8, 0, 0, 0, 0, 0, 0},\r
+ {rDI, val8, 0, 0, 0, 0, 0, 0},\r
+ {rBP, val8, 0, 0, 0, 0, 0, 0},\r
+ {rBX, val8, 0, 0, 0, 0, 0, 0},\r
+ {rBX, rSI, val16, 0, 0, 0, 0, 0},\r
+ {rBX, rDI, val16, 0, 0, 0, 0, 0},\r
+ {rBP, rSI, val16, 0, 0, 0, 0, 0},\r
+ {rBP, rDI, val16, 0, 0, 0, 0, 0},\r
+ {rSI, val16, 0, 0, 0, 0, 0, 0},\r
+ {rDI, val16, 0, 0, 0, 0, 0, 0},\r
+ {rBP, val16, 0, 0, 0, 0, 0, 0},\r
+ {rBX, val16, 0, 0, 0, 0, 0, 0},\r
+ };\r
+\r
+/* End of memory Look-up tables */\r
+\r
+/* The following flag bits are used to determine memory operand size\r
+ either by looking at the register involved, or by seeing the user\r
+ force the size with WORD PTR (etc.). They are put in variable\r
+ OpSize and used by the functions that encode the instruction.\r
+*/\r
+\r
+#define fByte 0x01\r
+#define fWord 0x02\r
+#define fDWord 0x04\r
+#define fFWord 0x08\r
+#define fNear 0x10\r
+#define fFar 0x20\r
+#define fShort 0x40\r
+#define fPtr 0x80 /* not currently used... */\r
+\r
+/* The following flag bits are used to determine if a register prefix\r
+ was specified as part of a memory address. The flag bits are set in\r
+ char variable OpPrefix.\r
+*/\r
+\r
+#define fDSp 0x01\r
+#define fESp 0x02\r
+#define fSSp 0x04\r
+#define fFSp 0x08\r
+#define fGSp 0x10\r
+#define fCSp 0x20\r
+\r
+/* END OF HEADER FILE */\r
projects / mmurtl / commitdiff