4 char *pci_func_desc(uint8_t class, uint8_t sub, uint8_t prog);
5 void pci_write_config(uint32_t base, uint8_t offset, uint32_t val);
6 uint32_t pci_read_config(uint32_t base, uint8_t offset);
17 uint8_t cachelinesize;
23 /* header type 0x00 */
25 struct pci_header header;
32 uint32_t cardbuscispointer;
33 uint16_t subsystemvendorid;
35 uint32_t expansionrombaseaddress;
36 uint32_t capabilities_pointer; /* only low 8 bits, remainder reserved */
38 uint8_t interrupt_line;
39 uint8_t interrupt_pin;
44 /* header type 0x01 */
46 struct pci_header header;
49 uint8_t primary_bus_number;
50 uint8_t secondary_bus_number;
51 uint8_t subordinate_bus_number;
52 uint8_t secondary_latency_timer;
55 uint16_t secondary_status;
57 uint16_t memory_limit;
58 uint16_t prefetchable_memory_base;
59 uint16_t prefetchable_memory_limit;
61 uint8_t iolimit_upper;
62 uint32_t capabilities_pointer; /* only low 8 bits, remainder reserved */
63 uint32_t expansion_rom;
64 uint8_t interrupt_line;
65 uint8_t interrupt_pin;
66 uint16_t bridge_control;
69 /* header type 0x02 */
71 struct pci_header header;
72 uint32_t cardbussocket;
75 uint16_t secondary_status;
78 uint8_t subordinate_bus_number;
79 uint8_t cardbus_latency_timer;
80 uint32_t memory_base0;
81 uint32_t memory_limit0;
82 uint32_t memory_base1;
83 uint32_t memory_limit1;
88 uint8_t interrupt_line;
89 uint8_t interrupt_pin;
90 uint16_t bridge_control;
91 uint16_t subsystem_device;
92 uint16_t subsystem_vendor;
93 uint32_t pccard16bitaddr;
97 struct pci_header header;
98 struct pci_general general;
99 struct pci_bridge bridge;
100 struct pci_cardbus cardbus;
104 union pci_device device;
105 struct pci_info *next;
106 struct pci_info *prev;
107 uint32_t base; /* base address of pci io registers */
112 extern struct pci_info *pci_devices;