--- /dev/null
+#ifndef PCI_H_
+#define PCI_H_ 1
+
+char *pci_func_desc(uint8_t class, uint8_t sub, uint8_t prog);
+void pci_write_config(uint32_t base, uint8_t offset, uint32_t val);
+uint32_t pci_read_config(uint32_t base, uint8_t offset);
+
+struct pci_header {
+ uint16_t vendorid;
+ uint16_t deviceid;
+ uint16_t command;
+ uint16_t status;
+ uint8_t revisionid;
+ uint8_t progif;
+ uint8_t subclass;
+ uint8_t classcode;
+ uint8_t cachelinesize;
+ uint8_t latencytimer;
+ uint8_t headertype;
+ uint8_t bist;
+};
+
+/* header type 0x00 */
+struct pci_general {
+ struct pci_header header;
+ uint32_t bar0;
+ uint32_t bar1;
+ uint32_t bar2;
+ uint32_t bar3;
+ uint32_t bar4;
+ uint32_t bar5;
+ uint32_t cardbuscispointer;
+ uint16_t subsystemvendorid;
+ uint16_t subsystemid;
+ uint32_t expansionrombaseaddress;
+ uint32_t capabilities_pointer; /* only low 8 bits, remainder reserved */
+ uint32_t reserved38;
+ uint8_t interrupt_line;
+ uint8_t interrupt_pin;
+ uint8_t mingrant;
+ uint8_t maxlatency;
+};
+
+/* header type 0x01 */
+struct pci_bridge {
+ struct pci_header header;
+ uint32_t bar0;
+ uint32_t bar1;
+ uint8_t primary_bus_number;
+ uint8_t secondary_bus_number;
+ uint8_t subordinate_bus_number;
+ uint8_t secondary_latency_timer;
+ uint8_t iobase;
+ uint8_t iolimit;
+ uint16_t secondary_status;
+ uint16_t memory_base;
+ uint16_t memory_limit;
+ uint16_t prefetchable_memory_base;
+ uint16_t prefetchable_memory_limit;
+ uint8_t iobase_upper;
+ uint8_t iolimit_upper;
+ uint32_t capabilities_pointer; /* only low 8 bits, remainder reserved */
+ uint32_t expansion_rom;
+ uint8_t interrupt_line;
+ uint8_t interrupt_pin;
+ uint16_t bridge_control;
+};
+
+/* header type 0x02 */
+struct pci_cardbus {
+ struct pci_header header;
+ uint32_t cardbussocket;
+ uint8_t capoffset;
+ uint8_t reserved;
+ uint16_t secondary_status;
+ uint8_t pci_bus;
+ uint8_t cardbus_bus;
+ uint8_t subordinate_bus_number;
+ uint8_t cardbus_latency_timer;
+ uint32_t memory_base0;
+ uint32_t memory_limit0;
+ uint32_t memory_base1;
+ uint32_t memory_limit1;
+ uint32_t io_base0;
+ uint32_t io_limit0;
+ uint32_t io_base1;
+ uint32_t io_limit1;
+ uint8_t interrupt_line;
+ uint8_t interrupt_pin;
+ uint16_t bridge_control;
+ uint16_t subsystem_device;
+ uint16_t subsystem_vendor;
+ uint32_t pccard16bitaddr;
+};
+
+union pci_device {
+ struct pci_header header;
+ struct pci_general general;
+ struct pci_bridge bridge;
+ struct pci_cardbus cardbus;
+};
+
+struct pci_info {
+ union pci_device device;
+ struct pci_info *next;
+ struct pci_info *prev;
+ uint32_t base; /* base address of pci io registers */
+ size_t bar_size[6];
+ void *bar_addr[6];
+};
+
+extern struct pci_info *pci_devices;
+
+void pci_init();
+
+#endif