1 /* 386 D-Group ASSEMBLER. Header file.
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2 Copyright 1992 R.A. Burgess
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5 /* The DASM parser returns a TOKEN type and fills in certain
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6 global variables with the values found. The token type is
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7 placed in Token as well as being returned to the caller.
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10 /* The following are the TOKEN types returned by the parser or
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11 the expression analyzer :
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14 #define ZERO 0 /* Parser returned NOTHING (blank or EOL) */
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15 #define INSTRU 1 /* 386 instruction. Number placed in TInst. */
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16 #define REGIST 2 /* 386 register is placed in TReg */
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17 #define SYMBOL 3 /* In symbol table. Sym number placed in TSymnum */
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18 #define LSYMBOL 4 /* In symbol table. LSym number placed in TSymnum */
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19 #define STRING 5 /* 'quoted' string of characters left in TString */
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20 #define NUMBER 6 /* Valid value placed in TNumber */
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21 #define NUMOFF 7 /* Valid TNumber derived from OFFSET (needs fix) */
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22 #define UNKSYM 8 /* Qualifies as a sym but not found. Left in TString */
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23 #define SYMOFF 9 /* Symbol offset value (from Expression analyzer) */
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24 #define ERROR 10 /* Bad char found in line. Line terminated by Parse(). */
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26 /* alphabetized list of reserved words excluding registers and
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27 instructions. They must be alphabetized for binary search
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28 function to work. They begin with #89 so they don't conflict
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29 with other token values. */
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31 #define nreserved 30
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32 #define srsvd 8 /* size of a reserved storage */
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33 #define nrsvd1 94 /* must be the first number of rgReserved */
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34 char rgReserved[nreserved][srsvd] = { /* 109 bytes */
\r
50 "INCLUDE", /* 109 */
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63 "VIRTUAL", /* 122 */
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64 "WORD", /* 123 up to 127 MAX */
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67 /* The following reserved "words" are recognized by Parse.
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68 This list MUST agree with the numbering of the table
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72 #define rALIGN 94 /* .ALIGN n - Align code segment */
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73 #define rBYTE 95 /* for forcing types on operands */
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74 #define rCODE 96 /* .CODE - begin/continue code segment */
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75 #define rDATA 97 /* .DATA - begin/continue data segment */
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76 #define rDB 98 /* storage of byte(s) or (strings) */
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77 #define rDD 99 /* double words */
\r
78 #define rDF 100 /* FWord (OFF:SEL) */
\r
79 #define rDUP 101 /* duplicated storage of DB, DW or DD */
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80 #define rDW 102 /* storage of words follows */
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81 #define rDWORD 103 /* for forcing types on operands */
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82 #define rEND 104 /* .END - file end - no more segments */
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83 #define rEQU 105 /* EQUATE for numbers/addresses only */
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84 #define rEXTRN 106 /* for EXTERNAL definition */
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85 #define rFAR 107 /* FAR operator for calls */
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86 #define rFWORD 108 /* for forcing types on operands */
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87 #define rINCLUDE 109 /* .INCLUDE - Include file for assembly */
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88 #define rNAME 110 /* .NAME to name a segment */
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89 #define rNEAR 111 /* NEAR operator for calls (default) */
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90 #define rOFFSET 112 /* offset in segment of ... */
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91 #define rPARA 113 /* PTR operator for mem ops */
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92 #define rPTR 114 /* PTR operator for mem ops */
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93 #define rPUBLIC 115 /* for PUBLIC declarations */
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94 #define rSEARCH 116 /* SEARCH command for Lib files */
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95 #define rSHORT 117 /* SHORT operator for relative jumps */
\r
96 #define rSTACK 118 /* .START - Entry point for execution */
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97 #define rSTART 119 /* .STACK - Sets initial stack size */
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98 #define rUSE16 120 /* .USE16 (16 bit segment) */
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99 #define rUSE32 121 /* .USE16 (16 bit segment) */
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100 #define rVIRTUAL 122 /* .VIRTUAL n - Data @ virtual address n */
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101 #define rWORD 123 /* WORD operator for mem ops */
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103 /* Special characters. They are treated as reserved words but are
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104 not searched alphabetically. They must maintain their ASCII
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105 values (other tokens are numbers "around" them).
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108 #define DOLLAR 0x24 /* 36 */
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109 #define SQUOTE 0x27 /* 39 */
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110 #define OPENRND 0x28 /* 40 */
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111 #define CLOSRND 0x29 /* 41 */
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112 #define STAR 0x2a /* 42 */
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113 #define PLUS 0x2b /* 43 */
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114 #define COMMA 0x2c /* 44 */
\r
115 #define MINUS 0x2d /* 45 */
\r
116 #define DOT 0x2e /* 46 */
\r
117 #define SLASH 0x2f /* 47 */
\r
118 #define COLON 0x3a /* 58 */
\r
119 #define SEMI 0x3b /* 59 */
\r
120 #define OPENSQR 0x5b /* 91 */
\r
121 #define CLOSSQR 0x5d /* 93 */
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123 /* The following bits identify symbol types in GST & LST */
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125 #define CLABEL 0x0001 /* Code label - SymPtr has Offset in Code seg */
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126 #define DLABEL 0x0002 /* Data label - SymPtr has Offset in Data seg */
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127 #define MACRO 0x0004 /* No offset associated - pts to string */
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128 #define sBYTE 0x0008 /* Data label for BYTE (8 bit) */
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129 #define sWORD 0x0010 /* Data label for WORD (16 bit) */
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130 #define sDWORD 0x0020 /* Data label for DWORD (32 bit) */
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131 #define sFWORD 0x0040 /* Data label for FWORD (48 bit) */
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132 #define tEXTRN 0x0080 /* Defined External, Public not found yet */
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133 #define tFAR 0x0100 /* Defined as FAR, default is near */
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134 #define tPUBLIC 0x0200 /* Defined as PUBLIC */
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137 /* This is an alphabetical array of all the 386 registers.
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138 It it used for a binary search for a register name. If
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139 the beginning number (128) is changed here you must make
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140 sure to change the define nreg1 to match to the search
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141 routine will give you the correct number They start at 128
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142 so they don't conflict with operand types in instruction table
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150 char rgreg[nregs][4] = { /* 176 bytes */
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238 /* This is an alaphebetical array of all the 386 instructions */
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239 /* It it used for a binary search for an instruction */
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242 #define sinst 7 /* size of a instruction storage */
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244 long rgInsLookUp[ninst+1]; /* Lookup for instruction table */
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246 char rginst[ninst][sinst] = { /* 1456 bytes */
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356 "LOOPNE", /* 101 */
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357 "LOOPNZ", /* 102 */
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390 "PUSHAD", /* 131 */
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392 "PUSHFD", /* 133 */
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426 "SETNAE", /* 165 */
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428 "SETNBE", /* 167 */
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432 "SETNGE", /* 171 */
\r
434 "SETNLE", /* 173 */
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581 #define xLOOPNE 101
\r
582 #define xLOOPNZ 102
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615 #define xPUSHAD 131
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617 #define xPUSHFD 133
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651 #define xSETNAE 165
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653 #define xSETNBE 167
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657 #define xSETNGE 171
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659 #define xSETNLE 173
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700 #define nrinst 80 /* number of float instructions */
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702 char rgrinst[nrinst][srinst] = { /* 560 bytes */
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716 "FDECSTP", /* 13 */
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729 "FINCSTP", /* 26 */
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752 "FNSTENV", /* 49 */
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758 "FRNDINT", /* 55 */
\r
763 "FSINCOS", /* 60 */
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777 "FUCOMPP", /* 74 */
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781 "FXTRACT", /* 78 */
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783 "FYL2XP1" }; /* 80 */
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786 /* END OF INSTRUCTIONS */
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788 /* Allowed Operand types for instruction sequences
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789 Start numbering at 61 so they don't conflict with
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790 token values or special characters */
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792 #define rel8 61 /* mem address within +/-127 bytes of currnt address */
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793 #define relW 62 /* mem address relative (WORD/DWORD) of current addr */
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794 #define iSAD 63 /* immediate segment address (seg16:offset16/32) */
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795 #define r8 64 /* Reg: AL, BL, CL, DL, AH, BH, CH, DH */
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796 #define r16 65 /* Reg: AX, BX, CX, DX, SP, BP, SI, DI */
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797 #define r32 66 /* Reg: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI */
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798 #define rREG 67 /* Any 8, 16 or 32 bit general register */
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799 #define rRGW 68 /* Any 16 or 32 bit general register */
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800 #define rACC 69 /* Reg: Accumulator AL, AX, EAX (any size) */
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801 #define rSEG 70 /* Reg: CS, DS, SS, ES, FS, GS */
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802 #define rCRG 71 /* Reg: CR0, CR2, CR3 */
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803 #define rDRG 72 /* Reg: DR0, DR1, DR2, DR3, DR6, DR7 */
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804 #define rTRG 73 /* Reg: TR6, TR7 */
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805 #define imm8 74 /* Immediate BYTE - UNSIGNED*/
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806 #define ims8 75 /* Immediate BYTE - Will be SIGN Extended!!! */
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807 #define imm16 76 /* Immediate WORD signed value */
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808 #define immX 77 /* immediate size value to match the other operand */
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809 #define rm8 78 /* r8 or memory address to BYTE */
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810 #define rm16 79 /* r16 or memory address to WORD */
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811 #define rRM 80 /* Any 8, 16 or 32 bit register or memory ref */
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812 #define rRMW 81 /* Any 16 or 32 bit register or memory ref */
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813 #define mem 82 /* Memory address. Any legal data mem reference */
\r
814 #define memF 83 /* Memory address of a 16:32 ptr value */
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815 #define moff 84 /* Memory address (Immediate, Disp only, Seg relative)*/
\r
816 #define immv3 85 /* immediate value 3 for INT 03 debug */
\r
817 #define immv1 86 /* immediate value 1 for some instructions (SHL etc.) */
\r
819 /* these are only used in the rgMEM32 table */
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821 #define val8 87 /* Indicates numeric value for displacement, */
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822 #define val16 88 /* immediate, address, etc. Used in memory model */
\r
823 #define val32 89 /* template. */
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826 /* Instruction sequence lookup table is made of:
\r
827 - Instruction number (from definitions above)
\r
828 - Opr1-3 are the legal operands for the instructions
\r
829 - Opc is base opcode.
\r
830 - Oprm is the ModR/M byte (if needed). It is partially filled in
\r
831 and used as indicated by Om1 below.
\r
832 - Opfx - Operand prefix and operand count for instruction.
\r
833 qP0F - Prefix Opc with 0x0f
\r
834 qUW - Use 0x66 prefix always
\r
835 qU16 - If USE16 prefix Opcodes with 0x66.
\r
836 qU32 - If USE32 prefix Opcodes with 0x66.
\r
838 - Om1 - Modifications or additions to OpCode to complete instruction:
\r
839 zMOP - Use Oprm as ModR/M byte (which is already filled in
\r
840 partially with Opcode in bits 3-5). If operand 1 is
\r
841 register, placed code in R/M field of ModR/M byte (bits 0-2).
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842 If operand 1 is mem, handle normally. In special case of
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843 AAD and AAM instructions Oprm is actually second byte of
\r
844 opcode (no operands to handle).
\r
845 zMR1 - Use Oprm as ModR/M byte. Register in operand 1
\r
846 must be encoded in REG/OPC field of ModR/M. If reg in
\r
847 operand 2 it must be incoded in R/M field.
\r
848 zMR2 - Use Oprm as ModR/M byte. Register in operand 2
\r
849 must be encoded in REG/OPC field of ModR/M. If reg in
\r
850 operand 1, it must be encoded in R/M field.
\r
851 zORD - OR Opc1 with 01 if WORD or DWORD reg/mem
\r
852 zAR1 - No ModRM, Add register code in operand 1 to Opc byte to
\r
853 complete the opcode.
\r
854 zAR2 - No ModRM, Add register code in operand 2 to Opc byte to
\r
855 complete the opcode.
\r
856 zRG1 - If register in operand 1, it must be encoded in
\r
857 REG/OPC field of ModR/M, else handle memory operand normally.
\r
858 zSIZ - This is not actually a modification to the instruction,
\r
859 but tells the assembler that the operand sizes will not
\r
860 match and that it's ok. The operand size should be the
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861 size of the first operand.
\r
865 /* Prefix instruction/operand count byte */
\r
872 /* OM1 instruction byte (Opcode Modifier/Special build instructions) */
\r
883 /* Certain table entries were added for optimization to ensure that
\r
884 the shortest instruction is used in all cases. This adds about
\r
885 50 lines to the table, but it's well worth the overhead!
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889 unsigned char rgINS[nrgINS][8] = { /* 338 * 8 = */
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891 /*Inst Opr1 Opr2 Opr3 Opfx Opc Oprm Om1 */
\r
893 {0 , 0, 0, 0, 0, 0, 0, 0 },
\r
894 {xAAA , 0, 0, 0, 0, 0x37, 0, 0 },
\r
895 {xAAD , 0, 0, 0, 0, 0xd5, 0x0A, zMOP },
\r
896 {xAAM , 0, 0, 0, 0, 0xd4, 0x0A, zMOP },
\r
897 {xADC , rACC, immX, 0, 0, 0x14, 0, zORD },
\r
898 {xADC , rRMW, imm8, 0, 0, 0x83, 0x10, zMOP },
\r
899 {xADC , rRM, immX, 0, 0, 0x80, 0x10, zMOP|zORD },
\r
900 {xADC , rRM, rREG, 0, 0, 0x10, 0, zMR2|zORD },
\r
901 {xADC , rREG, rRM, 0, 0, 0x12, 0, zMR1|zORD },
\r
903 {xADD , rRMW, ims8, 0, 0, 0x83, 0, zMOP },
\r
904 {xADD , rACC, immX, 0, 0, 0x04, 0, zORD },
\r
905 {xADD , rRM, immX, 0, 0, 0x80, 0, zMOP|zORD },
\r
906 {xADD , rREG, rRM, 0, 0, 0x02, 0, zMR1|zORD },
\r
907 {xADD , rRM, rREG, 0, 0, 0x00, 0, zMR2|zORD },
\r
909 {xAND , rRMW, ims8, 0, 0, 0x83, 0x20, zMOP },
\r
910 {xAND , rACC, immX, 0, 0, 0x24, 0, zORD },
\r
911 {xAND , rRM, immX, 0, 0, 0x80, 0x20, zMOP|zORD },
\r
912 {xAND , rREG, rRM, 0, 0, 0x22, 0, zMR1|zORD },
\r
913 {xAND , rRM, rREG, 0, 0, 0x20, 0, zMR2|zORD },
\r
915 {xARPL , rm16, r16, 0, 0, 0x63, 0, zMR2 },
\r
916 {xBOUND , rRMW, mem, 0, 0, 0x62, 0, zMR1 },
\r
917 {xBSF , rRGW, rRMW, 0, qP0F, 0xbc, 0, zMR1 },
\r
918 {xBSR , rRGW, rRMW, 0, qP0F, 0xbd, 0, zMR1 },
\r
919 {xBT , rRMW, rRGW, 0, qP0F, 0xa3, 0, zMR2 },
\r
920 {xBT , rRMW, imm8, 0, qP0F, 0xba, 0x20, zMOP },
\r
921 {xBTC , rRMW, rRGW, 0, qP0F, 0xbb, 0, zMR2 },
\r
922 {xBTC , rRMW, imm8, 0, qP0F, 0xba, 0x38, zMOP },
\r
923 {xBTR , rRMW, rRGW, 0, qP0F, 0xb3, 0, zMR2 },
\r
924 {xBTR , rRMW, imm8, 0, qP0F, 0xba, 0x30, zMOP },
\r
925 {xBTS , rRMW, rRGW, 0, qP0F, 0xab, 0, zMR2 },
\r
926 {xBTS , rRMW, imm8, 0, qP0F, 0xba, 0x28, zMOP },
\r
927 {xCALL , relW, 0, 0, 0, 0xe8, 0, 0 },
\r
928 {xCALL , rRMW, 0, 0, 0, 0xff, 0x10, zMOP },
\r
929 {xCALL , iSAD, 0, 0, 0, 0x9a, 0, 0 },
\r
930 {xCALL , memF, 0, 0, 0, 0xff, 0x18, zMOP },
\r
931 {xCBW , 0, 0, 0, qU32, 0x98, 0, 0 },
\r
932 {xCWDE , 0, 0, 0, qU16, 0x98, 0, 0 },
\r
933 {xCLC , 0, 0, 0, 0, 0xf8, 0, 0 },
\r
934 {xCLD , 0, 0, 0, 0, 0xfc, 0, 0 },
\r
935 {xCLI , 0, 0, 0, 0, 0xfa, 0, 0 },
\r
936 {xCLTS , 0, 0, 0, qP0F, 0x06, 0, 0 },
\r
937 {xCMC , 0, 0, 0, 0, 0xf5, 0, 0 },
\r
939 {xCMP , rRMW, ims8, 0, 0, 0x83, 0x38, zMOP },
\r
940 {xCMP , rACC, immX, 0, 0, 0x3c, 0, zORD },
\r
941 {xCMP , rRM, immX, 0, 0, 0x80, 0x38, zMOP|zORD },
\r
942 {xCMP , rREG, rRM, 0, 0, 0x3a, 0, zMR1|zORD },
\r
943 {xCMP , rRM, rREG, 0, 0, 0x38, 0, zMR2|zORD },
\r
945 {xCMPSB , 0, 0, 0, 0, 0xa6, 0, 0 },
\r
946 {xCMPSD , 0, 0, 0, 0, 0xa7, 0, 0 },
\r
947 {xCMPSW , 0, 0, 0, qUW, 0xa7, 0, 0 },
\r
948 {xCWD , 0, 0, 0, qUW, 0x99, 0, 0 },
\r
949 {xCDQ , 0, 0, 0, qU16, 0x99, 0, 0 },
\r
950 {xDAA , 0, 0, 0, 0, 0x27, 0, 0 },
\r
951 {xDAS , 0, 0, 0, 0, 0x2f, 0, 0 },
\r
952 {xDEC , rRGW, 0, 0, 0, 0x48, 0, zAR1 },
\r
953 {xDEC , rRM, 0, 0, 0, 0xfe, 0x08, zMOP|zORD },
\r
954 {xDIV , rRM, 0, 0, 0, 0xf6, 0x30, zMOP|zORD },
\r
955 {xENTER , imm16, imm8, 0, 0, 0xc8, 0, zSIZ },
\r
956 {xHLT , 0, 0, 0, 0, 0xf4, 0, 0 },
\r
957 {xIDIV , rRM, 0, 0, 0, 0xf6, 0x38, zMOP|zORD },
\r
958 {xIMUL , rRM, 0, 0, 0, 0xf6, 0x28, zMOP|zORD },
\r
959 {xIMUL , rRGW, rRMW, 0, qP0F, 0xaf, 0, zMR1 },
\r
960 {xIMUL , rRGW, rRMW, imm8, 0, 0x6b, 0, zMR1 },
\r
961 {xIMUL , rRGW, imm8, 0, 0, 0x6b, 0, zMR1|zSIZ },
\r
962 {xIMUL , rRGW, rRMW, immX, 0, 0x69, 0, zMR1 },
\r
963 {xIMUL , rRGW, immX, 0, 0, 0x69, 0, zMR1 },
\r
964 {xIN , rACC, imm8, 0, 0, 0xe4, 0, zORD|zSIZ },
\r
965 {xIN , rACC, rDX, 0, 0, 0xec, 0, zORD|zSIZ },
\r
966 {xINC , rRGW, 0, 0, 0, 0x40, 0, zAR1 },
\r
967 {xINC , rRM, 0, 0, 0, 0xfe, 0, zMOP|zORD },
\r
968 {xINSB , 0, 0, 0, 0, 0x6C, 0, 0 },
\r
969 {xINSD , 0, 0, 0, 0, 0x6D, 0, 0 },
\r
970 {xINSW , 0, 0, 0, qUW, 0x6D, 0, 0 },
\r
971 {xINT , immv3, 0, 0, 0, 0xcc, 0, 0 },
\r
972 {xINT , imm8, 0, 0, 0, 0xcd, 0, 0 },
\r
973 {xINTO , 0, 0, 0, 0, 0xce, 0, 0 },
\r
974 {xIRET , 0, 0, 0, qUW, 0xcf, 0, 0 },
\r
975 {xIRETD , 0, 0, 0, 0, 0xcf, 0, 0 },
\r
976 {xJA , rel8, 0, 0, 0, 0x77, 0, 0 },
\r
977 {xJA , relW, 0, 0, qP0F, 0x87, 0, 0 },
\r
978 {xJAE , rel8, 0, 0, 0, 0x73, 0, 0 },
\r
979 {xJAE , relW, 0, 0, qP0F, 0x83, 0, 0 },
\r
980 {xJB , rel8, 0, 0, 0, 0x72, 0, 0 },
\r
981 {xJB , relW, 0, 0, qP0F, 0x82, 0, 0 },
\r
982 {xJBE , rel8, 0, 0, 0, 0x76, 0, 0 },
\r
983 {xJBE , relW, 0, 0, qP0F, 0x86, 0, 0 },
\r
984 {xJC , rel8, 0, 0, 0, 0x72, 0, 0 },
\r
985 {xJC , relW, 0, 0, qP0F, 0x82, 0, 0 },
\r
986 {xJCXZ , rel8, 0, 0, 0, 0xe3, 0, 0 },
\r
987 {xJNBE , rel8, 0, 0, 0, 0x77, 0, 0 },
\r
988 {xJNBE , relW, 0, 0, qP0F, 0x87, 0, 0 },
\r
989 {xJNB , rel8, 0, 0, 0, 0x73, 0, 0 },
\r
990 {xJNB , relW, 0, 0, qP0F, 0x83, 0, 0 },
\r
991 {xJNC , rel8, 0, 0, 0, 0x73, 0, 0 },
\r
992 {xJNC , relW, 0, 0, qP0F, 0x83, 0, 0 },
\r
993 {xJNA , rel8, 0, 0, 0, 0x76, 0, 0 },
\r
994 {xJNA , relW, 0, 0, qP0F, 0x86, 0, 0 },
\r
995 {xJNAE , rel8, 0, 0, 0, 0x72, 0, 0 },
\r
996 {xJNAE , relW, 0, 0, qP0F, 0x82, 0, 0 },
\r
997 {xJECXZ , rel8, 0, 0, 0, 0xe3, 0, 0 },
\r
998 {xJE , rel8, 0, 0, 0, 0x74, 0, 0 },
\r
999 {xJE , relW, 0, 0, qP0F, 0x84, 0, 0 },
\r
1000 {xJG , rel8, 0, 0, 0, 0x7f, 0, 0 },
\r
1001 {xJG , relW, 0, 0, qP0F, 0x8f, 0, 0 },
\r
1002 {xJGE , rel8, 0, 0, 0, 0x7d, 0, 0 },
\r
1003 {xJGE , relW, 0, 0, qP0F, 0x8d, 0, 0 },
\r
1004 {xJNL , rel8, 0, 0, 0, 0x7d, 0, 0 },
\r
1005 {xJNL , relW, 0, 0, qP0F, 0x8d, 0, 0 },
\r
1006 {xJL , rel8, 0, 0, 0, 0x7c, 0, 0 },
\r
1007 {xJL , relW, 0, 0, qP0F, 0x8c, 0, 0 },
\r
1008 {xJNGE , rel8, 0, 0, 0, 0x7c, 0, 0 },
\r
1009 {xJNGE , relW, 0, 0, qP0F, 0x8c, 0, 0 },
\r
1010 {xJLE , rel8, 0, 0, 0, 0x7e, 0, 0 },
\r
1011 {xJLE , relW, 0, 0, qP0F, 0x8e, 0, 0 },
\r
1012 {xJNG , rel8, 0, 0, 0, 0x7e, 0, 0 },
\r
1013 {xJNG , relW, 0, 0, qP0F, 0x8e, 0, 0 },
\r
1014 {xJNE , rel8, 0, 0, 0, 0x75, 0, 0 },
\r
1015 {xJNE , relW, 0, 0, qP0F, 0x85, 0, 0 },
\r
1016 {xJNLE , rel8, 0, 0, 0, 0x7f, 0, 0 },
\r
1017 {xJNLE , relW, 0, 0, qP0F, 0x8f, 0, 0 },
\r
1018 {xJNO , rel8, 0, 0, 0, 0x71, 0, 0 },
\r
1019 {xJNO , relW, 0, 0, qP0F, 0x81, 0, 0 },
\r
1020 {xJNP , rel8, 0, 0, 0, 0x7b, 0, 0 },
\r
1021 {xJNP , relW, 0, 0, qP0F, 0x8b, 0, 0 },
\r
1022 {xJNS , rel8, 0, 0, 0, 0x79, 0, 0 },
\r
1023 {xJNS , relW, 0, 0, qP0F, 0x89, 0, 0 },
\r
1024 {xJNZ , rel8, 0, 0, 0, 0x75, 0, 0 },
\r
1025 {xJNZ , relW, 0, 0, qP0F, 0x85, 0, 0 },
\r
1026 {xJO , rel8, 0, 0, 0, 0x70, 0, 0 },
\r
1027 {xJO , relW, 0, 0, qP0F, 0x80, 0, 0 },
\r
1028 {xJP , rel8, 0, 0, 0, 0x7a, 0, 0 },
\r
1029 {xJP , relW, 0, 0, qP0F, 0x8a, 0, 0 },
\r
1030 {xJPO , rel8, 0, 0, 0, 0x7b, 0, 0 },
\r
1031 {xJPO , relW, 0, 0, qP0F, 0x8b, 0, 0 },
\r
1032 {xJPE , rel8, 0, 0, 0, 0x7a, 0, 0 },
\r
1033 {xJPE , relW, 0, 0, qP0F, 0x8a, 0, 0 },
\r
1034 {xJS , rel8, 0, 0, 0, 0x78, 0, 0 },
\r
1035 {xJS , relW, 0, 0, qP0F, 0x88, 0, 0 },
\r
1036 {xJZ , rel8, 0, 0, 0, 0x74, 0, 0 },
\r
1037 {xJZ , relW, 0, 0, qP0F, 0x84, 0, 0 },
\r
1038 {xJMP , rel8, 0, 0, 0, 0xeb, 0, 0 },
\r
1039 {xJMP , relW, 0, 0, 0, 0xe9, 0, 0 },
\r
1040 {xJMP , rRMW, 0, 0, 0, 0xff, 0x20, zMOP },
\r
1041 {xJMP , iSAD, 0, 0, 0, 0xea, 0, 0 },
\r
1042 {xJMP , memF, 0, 0, 0, 0xff, 0x28, zMOP },
\r
1043 {xLAHF , 0, 0, 0, 0, 0x9f, 0, 0 },
\r
1044 {xLAR , rRGW, rRMW, 0, qP0F, 0x02, 0, zMR1 },
\r
1045 {xLEA , rRGW, mem, 0, 0, 0x8d, 0, zMR1|zSIZ },
\r
1046 {xLEAVE , 0, 0, 0, 0, 0xc9, 0, 0 },
\r
1047 {xLGDT , memF, 0, 0, qP0F, 0x01, 0x10, zMOP },
\r
1048 {xLIDT , memF, 0, 0, qP0F, 0x01, 0x18, zMOP },
\r
1049 {xLDS , rRGW, memF, 0, 0, 0xc5, 0, zMR1 },
\r
1050 {xLSS , rRGW, memF, 0, qP0F, 0xb2, 0, zMR1 },
\r
1051 {xLES , rRGW, memF, 0, 0, 0xc4, 0, zMR1 },
\r
1052 {xLFS , rRGW, memF, 0, qP0F, 0xb4, 0, zMR1 },
\r
1053 {xLGS , rRGW, memF, 0, qP0F, 0xb5, 0, zMR1 },
\r
1054 {xLLDT , rm16, 0, 0, qP0F, 0x00, 0x10, zMOP },
\r
1055 {xLMSW , rm16, 0, 0, qP0F, 0x01, 0x30, zMOP },
\r
1056 {xLOCK , 0, 0, 0, 0, 0xf0, 0, 0 },
\r
1057 {xLODSB , 0, 0, 0, 0, 0xac, 0, 0 },
\r
1058 {xLODSD , 0, 0, 0, 0, 0xad, 0, 0 },
\r
1059 {xLODSW , 0, 0, 0, qUW, 0xad, 0, 0 },
\r
1060 {xLOOP , rel8, 0, 0, 0, 0xe2, 0, 0 },
\r
1061 {xLOOPE , rel8, 0, 0, 0, 0xe1, 0, 0 },
\r
1062 {xLOOPZ , rel8, 0, 0, 0, 0xe1, 0, 0 },
\r
1063 {xLOOPNE, rel8, 0, 0, 0, 0xe0, 0, 0 },
\r
1064 {xLOOPNZ, rel8, 0, 0, 0, 0xe0, 0, 0 },
\r
1065 {xLSL , rRGW, rRMW, 0, qP0F, 0x03, 0, zMR1 },
\r
1066 {xLTR , rm16, 0, 0, qP0F, 0x00, 0x18, zMOP },
\r
1067 {xMOV , rACC, moff, 0, 0, 0xA0, 0, zORD },
\r
1068 {xMOV , moff, rACC, 0, 0, 0xA2, 0, zORD },
\r
1069 {xMOV , r8, imm8, 0, 0, 0xb0, 0, zAR1 },
\r
1070 {xMOV , rRGW, immX, 0, 0, 0xb8, 0, zAR1 },
\r
1071 {xMOV , rREG, rRM, 0, 0, 0x8a, 0, zMR1|zORD },
\r
1072 {xMOV , rRM, rREG, 0, 0, 0x88, 0, zMR2|zORD },
\r
1073 {xMOV , rRM, immX, 0, 0, 0xc6, 0, zMR1|zORD },/*?*/
\r
1074 {xMOV , rm16, rSEG, 0, 0, 0x8c, 0, zMR2 },
\r
1075 {xMOV , rSEG, rm16, 0, 0, 0x8e, 0, zMR1 },
\r
1076 {xMOV , r32, rCRG, 0, qP0F, 0x20, 0, zMR2 },
\r
1077 {xMOV , rCRG, r32, 0, qP0F, 0x22, 0, zMR1 },
\r
1078 {xMOV , r32, rDRG, 0, qP0F, 0x21, 0, zMR2 },
\r
1079 {xMOV , rDRG, r32, 0, qP0F, 0x23, 0, zMR1 },
\r
1080 {xMOV , r32, rTRG, 0, qP0F, 0x24, 0, zMR2 },
\r
1081 {xMOV , rTRG, r32, 0, qP0F, 0x26, 0, zMR1 },
\r
1082 {xMOVSB , 0, 0, 0, 0, 0xa4, 0, 0 },
\r
1083 {xMOVSD , 0, 0, 0, 0, 0xa5, 0, 0 },
\r
1084 {xMOVSW , 0, 0, 0, qUW, 0xa5, 0, 0 },
\r
1085 {xMOVSX , r32, rm16, 0, qP0F, 0xbf, 0, zMR1|zSIZ },
\r
1086 {xMOVSX , rRGW, rm8, 0, qP0F, 0xbe, 0, zMR1|zSIZ },
\r
1087 {xMOVZX , r32, rm16, 0, qP0F, 0xb7, 0, zMR1|zSIZ },
\r
1088 {xMOVZX , rRGW, rm8, 0, qP0F, 0xb6, 0, zMR1|zSIZ },
\r
1089 {xMUL , rRM, 0, 0, 0, 0xf6, 0x20, zMOP|zORD },
\r
1090 {xNEG , rRM, 0, 0, 0, 0xf6, 0x18, zMOP|zORD },
\r
1091 {xNOP , 0, 0, 0, 0, 0x90, 0, 0 },
\r
1092 {xNOT , rRM, 0, 0, 0, 0xf6, 0x10, zMOP|zORD },
\r
1094 {xOR , rRMW, ims8, 0, 0, 0x83, 0x08, zMOP },
\r
1095 {xOR , rACC, immX, 0, 0, 0x0c, 0, zORD },
\r
1096 {xOR , rRM, immX, 0, 0, 0x80, 0x08, zMOP|zORD },
\r
1097 {xOR , rREG, rRM, 0, 0, 0x0a, 0, zMR1|zORD },
\r
1098 {xOR , rRM, rREG, 0, 0, 0x08, 0, zMR2|zORD },
\r
1100 {xOUT , imm8, rACC, 0, 0, 0xe6, 0, zORD },
\r
1101 {xOUT , rDX, rACC, 0, 0, 0xee, 0, zORD },
\r
1102 {xOUTSB , 0, 0, 0, 0, 0x6e, 0, 0 },
\r
1103 {xOUTSD , 0, 0, 0, 0, 0x6f, 0, 0 },
\r
1104 {xOUTSW , 0, 0, 0, qUW, 0x6f, 0, 0 },
\r
1105 {xPOP , mem, 0, 0, 0, 0x8f, 0, zMOP },
\r
1106 {xPOP , rRGW, 0, 0, 0, 0x58, 0, zAR1 },
\r
1107 {xPOP , rDS, 0, 0, 0, 0x1f, 0, 0 },
\r
1108 {xPOP , rES, 0, 0, 0, 0x07, 0, 0 },
\r
1109 {xPOP , rSS, 0, 0, 0, 0x17, 0, 0 },
\r
1110 {xPOP , rFS, 0, 0, qP0F, 0xa1, 0, 0 },
\r
1111 {xPOP , rGS, 0, 0, qP0F, 0xa9, 0, 0 },
\r
1112 {xPOPA , 0, 0, 0, 0, 0x61, 0, 0 },
\r
1113 {xPOPAD , 0, 0, 0, 0, 0x61, 0, 0 },
\r
1114 {xPOPF , 0, 0, 0, 0, 0x9d, 0, 0 },
\r
1115 {xPOPFD , 0, 0, 0, 0, 0x9d, 0, 0 },
\r
1116 {xPUSH , mem, 0, 0, 0, 0xff, 0x30, zMOP },
\r
1117 {xPUSH , rRGW, 0, 0, 0, 0x50, 0, zAR1 },
\r
1118 {xPUSH , ims8, 0, 0, 0, 0x6a, 0, 0 },
\r
1119 {xPUSH , immX, 0, 0, 0, 0x68, 0, 0 },
\r
1120 {xPUSH , rCS, 0, 0, 0, 0x0e, 0, 0 },
\r
1121 {xPUSH , rSS, 0, 0, 0, 0x16, 0, 0 },
\r
1122 {xPUSH , rDS, 0, 0, 0, 0x1e, 0, 0 },
\r
1123 {xPUSH , rES, 0, 0, 0, 0x06, 0, 0 },
\r
1124 {xPUSH , rFS, 0, 0, qP0F, 0xa0, 0, 0 },
\r
1125 {xPUSH , rGS, 0, 0, qP0F, 0xa8, 0, 0 },
\r
1126 {xPUSHA , 0, 0, 0, 0, 0x60, 0, 0 },
\r
1127 {xPUSHAD, 0, 0, 0, 0, 0x60, 0, 0 },
\r
1128 {xPUSHF , 0, 0, 0, 0, 0x9c, 0, 0 },
\r
1129 {xPUSHFD, 0, 0, 0, 0, 0x9c, 0, 0 },
\r
1130 {xRCL , rRM, immv1, 0, 0, 0xd0, 0x10, zMOP|zORD|zSIZ },
\r
1131 {xRCL , rRM, rCL, 0, 0, 0xd2, 0x10, zMOP|zORD|zSIZ },
\r
1132 {xRCL , rRM, imm8, 0, 0, 0xc0, 0x10, zMOP|zORD|zSIZ },
\r
1133 {xRCR , rRM, immv1, 0, 0, 0xd0, 0x18, zMOP|zORD|zSIZ },
\r
1134 {xRCR , rRM, rCL, 0, 0, 0xd2, 0x18, zMOP|zORD|zSIZ },
\r
1135 {xRCR , rRM, imm8, 0, 0, 0xc0, 0x18, zMOP|zORD|zSIZ },
\r
1136 {xROL , rRM, immv1, 0, 0, 0xd0, 0, zMOP|zORD|zSIZ },
\r
1137 {xROL , rRM, rCL, 0, 0, 0xd2, 0, zMOP|zORD|zSIZ },
\r
1138 {xROL , rRM, imm8, 0, 0, 0xc0, 0, zMOP|zORD|zSIZ },
\r
1139 {xROR , rRM, immv1, 0, 0, 0xd0, 0x08, zMOP|zORD|zSIZ },
\r
1140 {xROR , rRM, rCL, 0, 0, 0xd2, 0x08, zMOP|zORD|zSIZ },
\r
1141 {xROR , rRM, imm8, 0, 0, 0xc0, 0x08, zMOP|zORD|zSIZ },
\r
1142 {xREP , 0, 0, 0, 0, 0xf3, 0, 0 },
\r
1143 {xREPE , 0, 0, 0, 0, 0xf3, 0, 0 },
\r
1144 {xREPNE , 0, 0, 0, 0, 0xf2, 0, 0 },
\r
1145 {xRETN , 0, 0, 0, 0, 0xc3, 0, 0 },
\r
1146 {xRETN , imm16, 0, 0, 0, 0xc2, 0, 0 },
\r
1147 {xRETF , 0, 0, 0, 0, 0xcb, 0, 0 },
\r
1148 {xRETF , imm16, 0, 0, 0, 0xca, 0, 0 },
\r
1149 {xSAL , rRM, immv1, 0, 0, 0xd0, 0x20, zMOP|zORD|zSIZ },
\r
1150 {xSAL , rRM, rCL, 0, 0, 0xd2, 0x20, zMOP|zORD|zSIZ },
\r
1151 {xSAL , rRM, imm8, 0, 0, 0xc0, 0x20, zMOP|zORD|zSIZ },
\r
1152 {xSAR , rRM, immv1, 0, 0, 0xd0, 0x38, zMOP|zORD|zSIZ },
\r
1153 {xSAR , rRM, rCL, 0, 0, 0xd2, 0x38, zMOP|zORD|zSIZ },
\r
1154 {xSAR , rRM, imm8, 0, 0, 0xc0, 0x38, zMOP|zORD|zSIZ },
\r
1155 {xSHL , rRM, immv1, 0, 0, 0xd0, 0x20, zMOP|zORD|zSIZ },
\r
1156 {xSHL , rRM, rCL, 0, 0, 0xd2, 0x20, zMOP|zORD|zSIZ },
\r
1157 {xSHL , rRM, imm8, 0, 0, 0xc0, 0x20, zMOP|zORD|zSIZ },
\r
1158 {xSHR , rRM, immv1, 0, 0, 0xd0, 0x28, zMOP|zORD|zSIZ },
\r
1159 {xSHR , rRM, rCL, 0, 0, 0xd2, 0x28, zMOP|zORD|zSIZ },
\r
1160 {xSHR , rRM, imm8, 0, 0, 0xc0, 0x28, zMOP|zORD|zSIZ },
\r
1162 {xSBB , rRMW, ims8, 0, 0, 0x83, 0x18, zMOP },
\r
1163 {xSBB , rACC, immX, 0, 0, 0x1c, 0, zORD },
\r
1164 {xSBB , rRM, immX, 0, 0, 0x80, 0x18, zMOP|zORD },
\r
1165 {xSBB , rREG, rRM, 0, 0, 0x1a, 0, zMR1|zORD },
\r
1166 {xSBB , rRM, rREG, 0, 0, 0x18, 0, zMR2|zORD },
\r
1168 {xSCASB , 0, 0, 0, 0, 0xae, 0, 0 },
\r
1169 {xSCASD , 0, 0, 0, 0, 0xaf, 0, 0 },
\r
1170 {xSCASW , 0, 0, 0, qUW, 0xaf, 0, 0 },
\r
1171 {xSETA , rm8, 0, 0, qP0F, 0x97, 0, zRG1 },
\r
1172 {xSETAE , rm8, 0, 0, qP0F, 0x93, 0, zRG1 },
\r
1173 {xSETB , rm8, 0, 0, qP0F, 0x92, 0, zRG1 },
\r
1174 {xSETBE , rm8, 0, 0, qP0F, 0x96, 0, zRG1 },
\r
1175 {xSETC , rm8, 0, 0, qP0F, 0x92, 0, zRG1 },
\r
1176 {xSETE , rm8, 0, 0, qP0F, 0x94, 0, zRG1 },
\r
1177 {xSETG , rm8, 0, 0, qP0F, 0x9F, 0, zRG1 },
\r
1178 {xSETGE , rm8, 0, 0, qP0F, 0x9D, 0, zRG1 },
\r
1179 {xSETL , rm8, 0, 0, qP0F, 0x9C, 0, zRG1 },
\r
1180 {xSETLE , rm8, 0, 0, qP0F, 0x9E, 0, zRG1 },
\r
1181 {xSETNA , rm8, 0, 0, qP0F, 0x96, 0, zRG1 },
\r
1182 {xSETNAE, rm8, 0, 0, qP0F, 0x92, 0, zRG1 },
\r
1183 {xSETNB , rm8, 0, 0, qP0F, 0x93, 0, zRG1 },
\r
1184 {xSETNBE, rm8, 0, 0, qP0F, 0x97, 0, zRG1 },
\r
1185 {xSETNC , rm8, 0, 0, qP0F, 0x93, 0, zRG1 },
\r
1186 {xSETNE , rm8, 0, 0, qP0F, 0x95, 0, zRG1 },
\r
1187 {xSETNG , rm8, 0, 0, qP0F, 0x9E, 0, zRG1 },
\r
1188 {xSETNGE, rm8, 0, 0, qP0F, 0x9C, 0, zRG1 },
\r
1189 {xSETNL , rm8, 0, 0, qP0F, 0x9D, 0, zRG1 },
\r
1190 {xSETNLE, rm8, 0, 0, qP0F, 0x9F, 0, zRG1 },
\r
1191 {xSETNO , rm8, 0, 0, qP0F, 0x91, 0, zRG1 },
\r
1192 {xSETNP , rm8, 0, 0, qP0F, 0x9B, 0, zRG1 },
\r
1193 {xSETNS , rm8, 0, 0, qP0F, 0x99, 0, zRG1 },
\r
1194 {xSETNZ , rm8, 0, 0, qP0F, 0x95, 0, zRG1 },
\r
1195 {xSETO , rm8, 0, 0, qP0F, 0x90, 0, zRG1 },
\r
1196 {xSETP , rm8, 0, 0, qP0F, 0x9A, 0, zRG1 },
\r
1197 {xSETPE , rm8, 0, 0, qP0F, 0x9A, 0, zRG1 },
\r
1198 {xSETPO , rm8, 0, 0, qP0F, 0x9B, 0, zRG1 },
\r
1199 {xSETS , rm8, 0, 0, qP0F, 0x98, 0, zRG1 },
\r
1200 {xSETZ , rm8, 0, 0, qP0F, 0x94, 0, zRG1 },
\r
1201 {xSGDT , memF, 0, 0, qP0F, 0x01, 0, zMOP },
\r
1202 {xSIDT , memF, 0, 0, qP0F, 0x01, 0x08, zMOP },
\r
1203 {xSHLD , rRMW, rRGW, imm8, qP0F, 0xa4, 0, 0 },
\r
1204 {xSHLD , rRMW, rRGW, rCL, qP0F, 0xa5, 0, 0 },
\r
1205 {xSHRD , rRMW, rRGW, imm8, qP0F, 0xac, 0, 0 },
\r
1206 {xSHRD , rRMW, rRGW, rCL, qP0F, 0xad, 0, 0 },
\r
1207 {xSLDT , rm16, 0, 0, qP0F, 0x00, 0, zMOP },
\r
1208 {xSMSW , rm16, 0, 0, qP0F, 0x01, 0x20, zMOP },
\r
1209 {xSTC , 0, 0, 0, 0, 0xf9, 0, 0 },
\r
1210 {xSTI , 0, 0, 0, 0, 0xfb, 0, 0 },
\r
1211 {xSTD , 0, 0, 0, 0, 0xfd, 0, 0 },
\r
1212 {xSTOSB , 0, 0, 0, 0, 0xaa, 0, 0 },
\r
1213 {xSTOSD , 0, 0, 0, 0, 0xab, 0, 0 },
\r
1214 {xSTOSW , 0, 0, 0, qUW, 0xab, 0, 0 },
\r
1215 {xSTR , rm16, 0, 0, qP0F, 0x00, 0x08, zMOP },
\r
1217 {xSUB , rRMW, ims8, 0, 0, 0x83, 0x28, zMOP },
\r
1218 {xSUB , rACC, immX, 0, 0, 0x2c, 0, zORD },
\r
1219 {xSUB , rRM, immX, 0, 0, 0x80, 0x28, zMOP|zORD },
\r
1220 {xSUB , rREG, rRM, 0, 0, 0x2a, 0, zMR1|zORD },
\r
1221 {xSUB , rRM, rREG, 0, 0, 0x28, 0, zMR2|zORD },
\r
1223 {xTEST , rACC, immX, 0, 0, 0xa8, 0, zORD },
\r
1224 {xTEST , rRM, immX, 0, 0, 0xf6, 0, zMOP|zORD },
\r
1225 {xTEST , rREG, rRM, 0, 0, 0x84, 0, zMR1|zORD },
\r
1226 {xVERR , rm16, 0, 0, qP0F, 0x00, 0x20, zMOP },
\r
1227 {xVERW , rm16, 0, 0, qP0F, 0x00, 0x28, zMOP },
\r
1228 {xWAIT , 0, 0, 0, 0, 0x9b, 0, 0 },
\r
1229 {xXCHG , r16, rAX, 0, 0, 0x90, 0, zAR1 },
\r
1230 {xXCHG , rAX, r16, 0, 0, 0x90, 0, zAR2 },
\r
1231 {xXCHG , r32, rEAX, 0, 0, 0x90, 0, zAR1 },
\r
1232 {xXCHG , rEAX, r32, 0, 0, 0x90, 0, zAR2 },
\r
1233 {xXCHG , rRM, rREG, 0, 0, 0x86, 0, zMR2|zORD },
\r
1234 {xXCHG , rREG, rRM, 0, 0, 0x86, 0, zMR1|zORD },
\r
1235 {xXLAT , mem, 0, 0, 0, 0x00, 0, 0 },
\r
1236 {xXLATB , 0, 0, 0, 0, 0x00, 0, 0 },
\r
1238 {xXOR , rRMW, ims8, 0, 0, 0x83, 0x30, zMOP },
\r
1239 {xXOR , rACC, immX, 0, 0, 0x34, 0, zORD },
\r
1240 {xXOR , rRM, immX, 0, 0, 0x80, 0x30, zMOP|zORD },
\r
1241 {xXOR , rREG, rRM, 0, 0, 0x32, 0, zMR1|zORD },
\r
1242 {xXOR , rRM, rREG, 0, 0, 0x30, 0, zMR2|zORD },
\r
1245 /* END of instruction sequence definitions */
\r
1247 /* This table provides look-up instructions on building the ModR/M and
\r
1248 SIB bytes (optional) for all memory references.
\r
1249 THIS IS ONLY FOR MEMORY REFERENCES.
\r
1250 The Mod value in this table can be ORed to the ModR/M byte
\r
1251 and SS value in this table can be ORed to the SIB byte
\r
1252 for the instruction you're building.
\r
1256 #define fBase 0x01
\r
1257 #define fIndx 0x02 /* fScale = 1 by default when fIndx is present */
\r
1258 #define fScale2 0x04
\r
1259 #define fScale4 0x08
\r
1260 #define fScale8 0x10
\r
1261 #define fDisp8 0x20
\r
1262 #define fDisp32 0x40
\r
1267 U8 rgM32[20][4] = {
\r
1268 /* UseSIB Mod SS */
\r
1269 { 0, 0, 0x00, 0x00 },
\r
1270 { fBase, 0, 0x00, 0x00 },
\r
1271 { fBase | fIndx, 1, 0x04, 0x00 },
\r
1272 { fIndx | fScale2, 1, 0x04, 0x40 },
\r
1273 { fIndx | fScale4, 1, 0x04, 0x80 },
\r
1274 { fIndx | fScale8, 1, 0x04, 0xC0 },
\r
1275 { fDisp32, 0, 0x05, 0x00 },
\r
1276 { fBase | fIndx | fScale2, 1, 0x04, 0x40 },
\r
1277 { fBase | fIndx | fScale4, 1, 0x04, 0x80 },
\r
1278 { fBase | fIndx | fScale8, 1, 0x04, 0xC0 },
\r
1279 { fBase | fDisp8, 0, 0x40, 0x00 },
\r
1280 { fBase | fDisp32, 0, 0x80, 0x00 },
\r
1281 { fBase | fIndx | fDisp8, 1, 0x44, 0x00 },
\r
1282 { fBase | fIndx | fDisp32, 1, 0x84, 0x00 },
\r
1283 { fBase | fIndx | fScale2 | fDisp8, 1, 0x44, 0x40 },
\r
1284 { fBase | fIndx | fScale4 | fDisp8, 1, 0x44, 0x80 },
\r
1285 { fBase | fIndx | fScale8 | fDisp8, 1, 0x44, 0xC0 },
\r
1286 { fBase | fIndx | fScale2 | fDisp32, 1, 0x84, 0x40 },
\r
1287 { fBase | fIndx | fScale4 | fDisp32, 1, 0x84, 0x80 },
\r
1288 { fBase | fIndx | fScale8 | fDisp32, 1, 0x84, 0xC0 },
\r
1292 /* The following 16 bit addressing modes are recognized: */
\r
1293 /* UseSIB is always 0 in 16 bit addressing modes */
\r
1297 int rgM16[24][8] = {
\r
1299 /* UseSIB Mod SS */
\r
1300 {rBX, rSI, 0, 0, 0, 0, 0, 0},
\r
1301 {rBX, rDI, 0, 0, 0, 0, 0, 0},
\r
1302 {rBP, rSI, 0, 0, 0, 0, 0, 0},
\r
1303 {rBP, rDI, 0, 0, 0, 0, 0, 0},
\r
1304 {rSI, 0, 0, 0, 0, 0, 0, 0},
\r
1305 {rDI, 0, 0, 0, 0, 0, 0, 0},
\r
1306 {val16, 0, 0, 0, 0, 0, 0, 0},
\r
1307 {rBX, 0, 0, 0, 0, 0, 0, 0},
\r
1308 {rBX, rSI, val8, 0, 0, 0, 0, 0},
\r
1309 {rBX, rDI, val8, 0, 0, 0, 0, 0},
\r
1310 {rBP, rSI, val8, 0, 0, 0, 0, 0},
\r
1311 {rBP, rDI, val8, 0, 0, 0, 0, 0},
\r
1312 {rSI, val8, 0, 0, 0, 0, 0, 0},
\r
1313 {rDI, val8, 0, 0, 0, 0, 0, 0},
\r
1314 {rBP, val8, 0, 0, 0, 0, 0, 0},
\r
1315 {rBX, val8, 0, 0, 0, 0, 0, 0},
\r
1316 {rBX, rSI, val16, 0, 0, 0, 0, 0},
\r
1317 {rBX, rDI, val16, 0, 0, 0, 0, 0},
\r
1318 {rBP, rSI, val16, 0, 0, 0, 0, 0},
\r
1319 {rBP, rDI, val16, 0, 0, 0, 0, 0},
\r
1320 {rSI, val16, 0, 0, 0, 0, 0, 0},
\r
1321 {rDI, val16, 0, 0, 0, 0, 0, 0},
\r
1322 {rBP, val16, 0, 0, 0, 0, 0, 0},
\r
1323 {rBX, val16, 0, 0, 0, 0, 0, 0},
\r
1326 /* End of memory Look-up tables */
\r
1328 /* The following flag bits are used to determine memory operand size
\r
1329 either by looking at the register involved, or by seeing the user
\r
1330 force the size with WORD PTR (etc.). They are put in variable
\r
1331 OpSize and used by the functions that encode the instruction.
\r
1334 #define fByte 0x01
\r
1335 #define fWord 0x02
\r
1336 #define fDWord 0x04
\r
1337 #define fFWord 0x08
\r
1338 #define fNear 0x10
\r
1340 #define fShort 0x40
\r
1341 #define fPtr 0x80 /* not currently used... */
\r
1343 /* The following flag bits are used to determine if a register prefix
\r
1344 was specified as part of a memory address. The flag bits are set in
\r
1345 char variable OpPrefix.
\r
1355 /* END OF HEADER FILE */
\r
projects / mmurtl / blob